{"block":{"name":"chip","variant":null,"commit":"e92b79860e037483a3481cf7b6abda28d3bf4d21","commit_short":"e92b798","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/e92b79860e037483a3481cf7b6abda28d3bf4d21","revision_info":"GitHub Revision: [`e92b798`](https://github.com/lowrisc/opentitan/tree/e92b79860e037483a3481cf7b6abda28d3bf4d21)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-21T15:00:32Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_flash":{"max_time":201.23,"sim_time":2612.36404,"passed":3,"total":3,"percent":100.0},"chip_sw_example_rom":{"max_time":87.78,"sim_time":2212.176312,"passed":3,"total":3,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":175.3,"sim_time":2439.740664,"passed":3,"total":3,"percent":100.0},"chip_sw_example_concurrency":{"max_time":239.87,"sim_time":3335.60121,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":261.92,"sim_time":4837.699855999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":544.87,"sim_time":5465.15684,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":626.78,"sim_time":5748.495589,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":4626.83,"sim_time":30268.809157000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":772.91,"sim_time":11235.11015,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":4626.83,"sim_time":30268.809157000003,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":544.87,"sim_time":5465.15684,"passed":5,"total":5,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":12.21,"sim_time":249.60601,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":482.31000000000006,"sim_time":4389.561173,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":482.31000000000006,"sim_time":4389.561173,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":482.31000000000006,"sim_time":4389.561173,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":541.0,"sim_time":4945.571968,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":541.0,"sim_time":4945.571968,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":523.46,"sim_time":4081.62244,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":548.16,"sim_time":4328.9411150000005,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":603.96,"sim_time":5019.193234,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":2456.45,"sim_time":13401.895779999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":1337.81,"sim_time":8956.386343,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":839.08,"sim_time":8818.715096000002,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":126,"total":128,"percent":98.4375},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":312.35,"sim_time":5296.069708,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":312.35,"sim_time":5296.069708,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":252.94,"sim_time":2715.578484,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":488.17999999999995,"sim_time":7538.46778,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":224.67,"sim_time":3112.49339,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":1249.13,"sim_time":15823.420034,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":473.04,"sim_time":6830.975606,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":272.47,"sim_time":4744.412322,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1015.01,"sim_time":12684.392634,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_pattgen_ios":{"tests":{"chip_sw_pattgen_ios":{"max_time":220.38,"sim_time":3128.376624,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pwm_pulses":{"tests":{"chip_sw_sleep_pwm_pulses":{"max_time":1139.04,"sim_time":9589.738353,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":591.53,"sim_time":5647.750954,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":591.53,"sim_time":5647.750954,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":796.96,"sim_time":8776.0654,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":2049.15,"sim_time":13681.046439,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":498.46,"sim_time":4109.850283,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":782.47,"sim_time":6301.511171,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5017.69,"sim_time":18704.722347,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":283.93,"sim_time":3134.410142,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1036.11,"sim_time":7553.150002,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":280.6,"sim_time":3473.1992659999996,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1813.2,"sim_time":10526.317035,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":302.81,"sim_time":3953.59892,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":512.53,"sim_time":5191.026691,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":240.02000000000004,"sim_time":2741.71004,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":239.89,"sim_time":2781.758718,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":732.06,"sim_time":9481.321104,"passed":3,"total":5,"percent":60.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":330.36,"sim_time":5011.26501,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":8,"percent":75.0},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":219.32,"sim_time":2727.90642,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":330.36,"sim_time":5011.26501,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_smoketest":{"tests":{"chip_sw_flash_scrambling_smoketest":{"max_time":214.12,"sim_time":3355.680215,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_smoketest":{"max_time":257.71,"sim_time":3117.476032,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":267.45,"sim_time":3540.4759449999997,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":215.29,"sim_time":2413.13952,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":221.34,"sim_time":2608.86725,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":1052.89,"sim_time":6555.286696,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":252.18999999999997,"sim_time":3165.110267,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":273.82,"sim_time":3440.279244,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":249.55,"sim_time":3154.8739649999998,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":1717.0,"sim_time":10361.8632,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":431.32,"sim_time":6802.131992,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":459.56,"sim_time":6949.201224,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":215.97,"sim_time":3782.121512,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":256.64,"sim_time":3019.6419619999997,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":211.65,"sim_time":2734.916903,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":195.02,"sim_time":2845.801732,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":279.05,"sim_time":2901.151398,"passed":3,"total":3,"percent":100.0}},"passed":51,"total":51,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":227.96,"sim_time":3640.20217,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":436.69,"sim_time":4473.6920310000005,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":12283.69,"sim_time":62777.458159999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":3836.36,"sim_time":15544.729164999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":138.27258190326393,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":299.19,"sim_time":3286.531,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":299.38,"sim_time":3324.665,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":11499.67,"sim_time":55082.745092,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":12092.51,"sim_time":56818.690676,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":258.08,"sim_time":3368.910166,"passed":4,"total":30,"percent":13.333333333333334}},"passed":4,"total":30,"percent":13.333333333333334},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":258.08,"sim_time":3368.910166,"passed":4,"total":30,"percent":13.333333333333334}},"passed":4,"total":30,"percent":13.333333333333334},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":4626.83,"sim_time":30268.809157000003,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":4546.3,"sim_time":27957.824114,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":261.92,"sim_time":4837.699855999999,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":544.87,"sim_time":5465.15684,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":4626.83,"sim_time":30268.809157000003,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":4546.3,"sim_time":27957.824114,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":261.92,"sim_time":4837.699855999999,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":544.87,"sim_time":5465.15684,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":75.77,"sim_time":2497.910707,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":8.07,"sim_time":59.171202,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":108.6,"sim_time":10016.130118000001,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":93.56,"sim_time":6153.074589,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":50.16,"sim_time":595.308553,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":503.22,"sim_time":57827.750574,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":493.98,"sim_time":35942.411786,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":58.53,"sim_time":1195.242704,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":47.89,"sim_time":1270.1452960000001,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":87.86,"sim_time":2231.593761,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":47.89,"sim_time":1270.1452960000001,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":126.17,"sim_time":3482.8905529999997,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":955.82,"sim_time":78494.514119,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":75.97,"sim_time":2643.4026910000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":671.49,"sim_time":23347.725839000002,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":646.11,"sim_time":18093.05878,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":702.79,"sim_time":8769.859257999999,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":572.33,"sim_time":7558.0330619999995,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":3836.36,"sim_time":15544.729164999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":3587.21,"sim_time":29940.838035999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":3951.62,"sim_time":14812.578441,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":170.86563921999186,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":11.920537157915533,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":10.473113160580397,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":11.523838791064918,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":12.051891247741878,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":62.96394219994545,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":14.783829620108008,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":12.040669867768884,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":11.537098187953234,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":11.692226856946945,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":179.58002407755703,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":16.507558955810964,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":17.936460629105568,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":17.93774489685893,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":18.2125088525936,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":103.86920543573797,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":18.62213141284883,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":22.368108014576137,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":27.590380730107427,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":20.91240107268095,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":140.26379603985697,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":21.453398630954325,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":22.155460358597338,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":35.4834866868332,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":47.14648560248315,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":131.45891228783876,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":62.47999884653836,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":26.23680446576327,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":34.7703393958509,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":22.934213838540018,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":184.90838062111288,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":16.98962051421404,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":10.981622453778982,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":11.219176145270467,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":11.266009178943932,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":7995.7300000000005,"sim_time":30646.755454,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":7851.299999999999,"sim_time":29956.78895,"passed":2,"total":3,"percent":66.66666666666667},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":7966.460000000001,"sim_time":28641.459304,"passed":3,"total":3,"percent":100.0}},"passed":8,"total":9,"percent":88.88888888888889},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":4197.92,"sim_time":16610.621369,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1667359797284,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1667359797284,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":208.09,"sim_time":2959.970762,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":283.93,"sim_time":3134.410142,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":258.3,"sim_time":3376.255752,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":269.92,"sim_time":3009.8451299999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":2233.25,"sim_time":12484.676807,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":239.25,"sim_time":3093.455143,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":456.91,"sim_time":5140.475427,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":724.24,"sim_time":5744.874888,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":385.5,"sim_time":4239.5768880000005,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":524.98,"sim_time":4807.470235999999,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":254.64,"sim_time":3429.732886,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1784.19,"sim_time":17170.196166,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":440.85,"sim_time":4890.484716,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":285.97,"sim_time":2831.101336,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":14400.161831110718,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1495.36,"sim_time":7759.721076000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1384.71,"sim_time":7620.966058,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":1092.54,"sim_time":8366.17972,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":14400.161792295983,"sim_time":0.0,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":379.01,"sim_time":4166.8137209999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":431.32,"sim_time":6802.131992,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":379.01,"sim_time":4166.8137209999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":561.4,"sim_time":7837.556,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":561.4,"sim_time":7837.556,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":441.72,"sim_time":7514.4696699999995,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":423.91,"sim_time":4757.4497949999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":804.77,"sim_time":5954.3112249999995,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":269.92,"sim_time":3009.8451299999997,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":233.05,"sim_time":3017.277208,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":216.76,"sim_time":2891.600584,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":410.34,"sim_time":5023.7073,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":297.18,"sim_time":4883.312650000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":425.33,"sim_time":4875.5683930000005,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":422.2,"sim_time":4625.541434999999,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":1144.7,"sim_time":11870.159599999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":511.33000000000004,"sim_time":4733.3273580000005,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":482.6499999999999,"sim_time":4683.276044,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":486.31000000000006,"sim_time":3702.09925,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":461.4,"sim_time":4820.30483,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":515.88,"sim_time":4816.080464,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":533.03,"sim_time":4754.068952,"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":796.96,"sim_time":8776.0654,"passed":3,"total":3,"percent":100.0}},"passed":21,"total":21,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":421.42,"sim_time":6286.766456,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":486.31000000000006,"sim_time":3702.09925,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":461.4,"sim_time":4820.30483,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":498.46,"sim_time":4109.850283,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":782.47,"sim_time":6301.511171,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5017.69,"sim_time":18704.722347,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":283.93,"sim_time":3134.410142,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1036.11,"sim_time":7553.150002,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":280.6,"sim_time":3473.1992659999996,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1813.2,"sim_time":10526.317035,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":302.81,"sim_time":3953.59892,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":512.53,"sim_time":5191.026691,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":240.02000000000004,"sim_time":2741.71004,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":206.97,"sim_time":3306.618269,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":503.2,"sim_time":4850.3402510000005,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":846.45,"sim_time":7099.442504,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":5057.63,"sim_time":25040.467041,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":225.12,"sim_time":3118.2924160000002,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":229.43,"sim_time":3449.586226,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":1319.99,"sim_time":10853.760139,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":265.34,"sim_time":3392.686025,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":501.42999999999995,"sim_time":4900.4885,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1504.42,"sim_time":22688.6829,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":28800.17739421595,"sim_time":0.0,"passed":2,"total":3,"percent":66.66666666666667}},"passed":32,"total":33,"percent":96.96969696969697},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":796.96,"sim_time":8776.0654,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":464.94,"sim_time":4742.18396,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":400.56,"sim_time":3855.2534640000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1495.36,"sim_time":7759.721076000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2916.97,"sim_time":23950.239032,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":309.34,"sim_time":4211.119360000001,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":557.78,"sim_time":6501.769376,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":257.38,"sim_time":3312.301429,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":8009.4400000000005,"sim_time":33103.066605,"passed":10,"total":10,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":229.32,"sim_time":2632.8256979999996,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":1051.78,"sim_time":8221.677432,"passed":3,"total":3,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":229.32,"sim_time":2632.8256979999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2916.97,"sim_time":23950.239032,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":206.29,"sim_time":3198.279275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init":{"tests":{"chip_sw_flash_init":{"max_time":1610.31,"sim_time":21980.3524,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_host_access":{"tests":{"chip_sw_flash_ctrl_access":{"max_time":809.24,"sim_time":5494.8163779999995,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":782.47,"sim_time":6301.511171,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_ctrl_ops":{"tests":{"chip_sw_flash_ctrl_ops":{"max_time":505.14000000000004,"sim_time":4462.119463000001,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":498.46,"sim_time":4109.850283,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_rma_unlocked":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4901.36,"sim_time":44384.902651000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_scramble":{"tests":{"chip_sw_flash_init":{"max_time":1610.31,"sim_time":21980.3524,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_idle_low_power":{"tests":{"chip_sw_flash_ctrl_idle_low_power":{"max_time":289.0,"sim_time":3617.0289860000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_keymgr_seeds":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_creator_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_creator_seed_wipe_on_rma":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4901.36,"sim_time":44384.902651000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_owner_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_wr_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_seed_hw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_escalate_en":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_flash_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":391.61,"sim_time":9497.24791,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"tests":{"chip_sw_flash_ctrl_clock_freqs":{"max_time":748.04,"sim_time":5520.950323,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_escalation_reset":{"tests":{"chip_sw_flash_crash_alert":{"max_time":550.79,"sim_time":6604.177182,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"tests":{"chip_sw_flash_crash_alert":{"max_time":550.79,"sim_time":6604.177182,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":252.08,"sim_time":3238.4083280000004,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":280.6,"sim_time":3473.1992659999996,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":233.05,"sim_time":3017.277208,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":1337.67,"sim_time":8782.410601,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":896.91,"sim_time":5349.6421119999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":489.39,"sim_time":4355.102974,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":572.17,"sim_time":5770.7902300000005,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":536.76,"sim_time":5106.680911,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":478.73,"sim_time":4432.179152,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":1813.2,"sim_time":10526.317035,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"tests":{"chip_sw_keymgr_sideload_kmac":{"max_time":1852.98,"sim_time":11342.288696,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":2233.25,"sim_time":12484.676807,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"tests":{"chip_sw_keymgr_sideload_otbn":{"max_time":3298.17,"sim_time":13667.506315999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":236.6,"sim_time":3188.92156,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":285.27,"sim_time":3180.57905,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":302.81,"sim_time":3953.59892,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":233.32,"sim_time":3016.67832,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":1489.25,"sim_time":8319.417988,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":216.76,"sim_time":2891.600584,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":456.91,"sim_time":5140.475427,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":1249.13,"sim_time":15823.420034,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":272.47,"sim_time":4744.412322,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1015.01,"sim_time":12684.392634,"passed":5,"total":5,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":200.06,"sim_time":2886.555026,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_key_derivation_prod":{"max_time":1917.56,"sim_time":11520.345293,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":247.21,"sim_time":3181.112376,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_rma_unlocked":{"max_time":4901.36,"sim_time":44384.902651000004,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":324.79,"sim_time":3365.8063119999997,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":714.61,"sim_time":6503.9729529999995,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":848.08,"sim_time":7494.4147920000005,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":723.12,"sim_time":7088.060673999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":485.08000000000004,"sim_time":9412.961334000001,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":773.57,"sim_time":8306.787197,"passed":3,"total":3,"percent":100.0},"chip_prim_tl_access":{"max_time":391.61,"sim_time":9497.24791,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":421.42,"sim_time":6286.766456,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":511.33000000000004,"sim_time":4733.3273580000005,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":482.6499999999999,"sim_time":4683.276044,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":486.31000000000006,"sim_time":3702.09925,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":461.4,"sim_time":4820.30483,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":515.88,"sim_time":4816.080464,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":533.03,"sim_time":4754.068952,"passed":3,"total":3,"percent":100.0},"chip_tap_straps_dev":{"max_time":1249.13,"sim_time":15823.420034,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":272.47,"sim_time":4744.412322,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1015.01,"sim_time":12684.392634,"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":409.04,"sim_time":8351.794815000001,"passed":0,"total":3,"percent":0.0}},"passed":74,"total":84,"percent":88.0952380952381},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":178.01,"sim_time":3362.316095,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":135.42,"sim_time":3470.034135,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":130.48,"sim_time":3577.625451,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":206.74,"sim_time":3819.74281,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":2429.08,"sim_time":33047.087797,"passed":3,"total":3,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":409.04,"sim_time":8351.794815000001,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":1272.41,"sim_time":26394.634644,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":954.83,"sim_time":10714.876224,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":926.28,"sim_time":11271.597085000001,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":584.82,"sim_time":6600.060775,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":2429.08,"sim_time":33047.087797,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":15,"percent":40.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":1377.09,"sim_time":25751.456615,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":111.85,"sim_time":2769.458107,"passed":3,"total":3,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":156.77393561508507,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":5,"total":9,"percent":55.55555555555556},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":4674.63,"sim_time":17876.510192,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5017.69,"sim_time":18704.722347,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":804.77,"sim_time":5954.3112249999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":804.77,"sim_time":5954.3112249999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":804.77,"sim_time":5954.3112249999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":429.89,"sim_time":4114.438301,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_flash_init":{"max_time":1610.31,"sim_time":21980.3524,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":429.89,"sim_time":4114.438301,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":574.65,"sim_time":5497.105332,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":207.16,"sim_time":2931.986319,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_flash_init":{"max_time":1610.31,"sim_time":21980.3524,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":429.89,"sim_time":4114.438301,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2038.1,"sim_time":12058.969841,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":574.65,"sim_time":5497.105332,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":207.16,"sim_time":2931.986319,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":415.29,"sim_time":4431.0443080000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":200.06,"sim_time":2886.555026,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":324.79,"sim_time":3365.8063119999997,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":714.61,"sim_time":6503.9729529999995,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":848.08,"sim_time":7494.4147920000005,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":723.12,"sim_time":7088.060673999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":1201.73,"sim_time":32210.376062000003,"passed":14,"total":15,"percent":93.33333333333333},"chip_prim_tl_access":{"max_time":391.61,"sim_time":9497.24791,"passed":3,"total":3,"percent":100.0}},"passed":26,"total":30,"percent":86.66666666666667},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":391.61,"sim_time":9497.24791,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":1212.75,"sim_time":8318.237570000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":265.44,"sim_time":6393.799928,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1182.92,"sim_time":24369.917043,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":293.39,"sim_time":6986.700535,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":500.62999999999994,"sim_time":7582.240125,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":593.46,"sim_time":8254.523783,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1327.53,"sim_time":24638.350664,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":1266.54,"sim_time":15203.383084000001,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":561.4,"sim_time":7837.556,"passed":0,"total":3,"percent":0.0}},"passed":2,"total":6,"percent":33.333333333333336},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":1347.37,"sim_time":11969.749076,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":503.52,"sim_time":5135.278157,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_aon_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":265.44,"sim_time":6393.799928,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":399.04,"sim_time":5481.709768,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":2904.25,"sim_time":32782.009691,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":469.16,"sim_time":8394.174732000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":182.64,"sim_time":3192.563315,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":2414.52,"sim_time":22356.452208,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1095.76,"sim_time":8430.504713,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1369.37,"sim_time":12965.777831,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":2805.75,"sim_time":36078.269071999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":258.68,"sim_time":3468.4750639999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":485.08000000000004,"sim_time":9412.961334000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":485.08000000000004,"sim_time":9412.961334000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1369.37,"sim_time":12965.777831,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":2414.52,"sim_time":22356.452208,"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_wdog_reset":{"max_time":503.52,"sim_time":5135.278157,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":431.32,"sim_time":6802.131992,"passed":3,"total":3,"percent":100.0}},"passed":10,"total":12,"percent":83.33333333333333},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":360.54,"sim_time":4555.883532,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":699.41,"sim_time":7416.622885,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":383.29,"sim_time":4578.2484,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1784.19,"sim_time":17170.196166,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":251.81,"sim_time":3104.0381519999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1384.71,"sim_time":7620.966058,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":732.82,"sim_time":5143.506904,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":674.69,"sim_time":5470.235712000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":257.88,"sim_time":3136.6902459999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":207.16,"sim_time":2931.986319,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":699.41,"sim_time":7416.622885,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":699.41,"sim_time":7416.622885,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":1406.67,"sim_time":18688.953132,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":1220.28,"sim_time":13979.56272,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":360.54,"sim_time":4555.883532,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":310.6,"sim_time":3393.5109199999997,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":473.04,"sim_time":6621.186732,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":272.47,"sim_time":4744.412322,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":409.04,"sim_time":8351.794815000001,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":724.24,"sim_time":5744.874888,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":385.5,"sim_time":4239.5768880000005,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":524.98,"sim_time":4807.470235999999,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":235.66,"sim_time":3067.5713760000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":225.96,"sim_time":3186.9393769999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":3836.36,"sim_time":15544.729164999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":744.39,"sim_time":7677.481987,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":280.96,"sim_time":2951.7862480000003,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":287.88,"sim_time":3394.385179,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":242.59999999999997,"sim_time":3640.7409759999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":574.65,"sim_time":5497.105332,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":512.53,"sim_time":5191.026691,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":557.78,"sim_time":8254.057966,"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":666.03,"sim_time":9296.601683,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":773.57,"sim_time":8306.787197,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0},"chip_sw_data_integrity_escalation":{"max_time":591.53,"sim_time":5647.750954,"passed":6,"total":6,"percent":100.0}},"passed":98,"total":106,"percent":92.45283018867924},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1095.76,"sim_time":8430.504713,"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1607.8,"sim_time":23435.708709,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":227.48,"sim_time":3616.4606009999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":356.49,"sim_time":3799.900168,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":500.6,"sim_time":5040.757106,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1607.8,"sim_time":23435.708709,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1607.8,"sim_time":23435.708709,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3209.44,"sim_time":20604.628837,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3209.44,"sim_time":20604.628837,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":415.48,"sim_time":5812.40423,"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1667359797284,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":173.61,"sim_time":3127.41408,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":205.02,"sim_time":3169.363238,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":376.34,"sim_time":4030.2857000000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":379.61,"sim_time":3733.55484,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":1379.95,"sim_time":8172.637284,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":7152.37,"sim_time":32647.901449999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":2410.86,"sim_time":12177.791328,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":262.66,"sim_time":3128.83919,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1554,"total":1799,"percent":86.38132295719845},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":270.78,"sim_time":3139.71767,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":167.0,"sim_time":2689.179664,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336}},"passed":4,"total":6,"percent":66.66666666666667},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":16476.06,"sim_time":72117.235844,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":1471.91,"sim_time":6933.4878,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":603.49,"sim_time":7201.909672000001,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":317.35,"sim_time":5062.183767,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":746.7,"sim_time":7472.963052,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":19.039586859755218,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":17.935012463480234,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":18.579567464999855,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":110.05595691967756,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":337.58,"sim_time":3566.420205,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":430.09,"sim_time":3149.745727,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":918.15,"sim_time":5129.641608,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":1584.68,"sim_time":8568.225328,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":307.17,"sim_time":2548.300249,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_memory_protection":{"tests":{"chip_sw_flash_ctrl_mem_protection":{"max_time":801.37,"sim_time":5725.463053,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":186.76,"sim_time":3111.4353939999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":210.53,"sim_time":2619.571854,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":460.71,"sim_time":6688.07538,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":501.3299999999999,"sim_time":5808.238865,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1369.37,"sim_time":12965.777831,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":603.49,"sim_time":7201.909672000001,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":317.35,"sim_time":5062.183767,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":746.7,"sim_time":7472.963052,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":444.35,"sim_time":5817.108818,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":649.93,"sim_time":6360.034629,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.168333273381,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.168333273381,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":267.74,"sim_time":3378.1587910000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":541.0,"sim_time":4945.571968,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":3349.65,"sim_time":18359.19054,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":135,"total":159,"percent":84.90566037735849},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sival_flash_info_access":{"max_time":289.57,"sim_time":3454.143748,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":533.92,"sim_time":5316.2946600000005,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":9.02,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":209.14,"sim_time":3720.985635,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":310.31,"sim_time":3395.356404,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":315.87,"sim_time":3830.58344,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":11.725330837070942,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_ctrl_write_clear":{"max_time":290.21,"sim_time":3276.41985,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_flash_erase":{"max_time":880.9,"sim_time":10010.320001,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":10086.87,"sim_time":46051.085114,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_disjoint":{"max_time":10800.163497279398,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":20,"total":31,"percent":64.51612903225806}},"passed":20,"total":31,"percent":64.51612903225806}},"coverage":{"code":{"block":null,"line_statement":94.77,"branch":94.99,"condition_expression":93.28,"toggle":91.58,"fsm":57.14},"assertion":98.0,"functional":99.39},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.20268817685967204168899950508421522173206697748901351387237125484959835596998","seed":20268817685967204168899950508421522173206697748901351387237125484959835596998,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3360.548410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.15914595772622183880489555019554184018125549711311957738038403312978610181069","seed":15914595772622183880489555019554184018125549711311957738038403312978610181069,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 2951.786248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.1193081027243177605965116522610453069647572190265514775191278217032728524228","seed":1193081027243177605965116522610453069647572190265514775191278217032728524228,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 2891.814964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.74828604842774625386192221852750657130916458340243471376251514245055898981834","seed":74828604842774625386192221852750657130916458340243471376251514245055898981834,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3317.854530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"1.chip_sw_flash_ctrl_lc_rw_en.74044341915464361849358113912194935316648668964005314531285420147768303787342","seed":74044341915464361849358113912194935316648668964005314531285420147768303787342,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3352.120184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"2.chip_sw_flash_ctrl_lc_rw_en.11998939803817618505902242169636321754842111241598387824379995019754290036112","seed":11998939803817618505902242169636321754842111241598387824379995019754290036112,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3181.112376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.46650060521807704347824721373336890419363207221141166969749028800841876877965","seed":46650060521807704347824721373336890419363207221141166969749028800841876877965,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6349.852136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.100329686727823776001783995647548336591094180337389279721135707054887792802071","seed":100329686727823776001783995647548336591094180337389279721135707054887792802071,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6507.370184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.25255968146922343944001691656388036465706955249228082338836239255791272162841","seed":25255968146922343944001691656388036465706955249228082338836239255791272162841,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7088.060674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.46942007668142458326432080494066826888824611434170920260768451780799085442988","seed":46942007668142458326432080494066826888824611434170920260768451780799085442988,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 2619.571854 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2619.571854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.107620229815429275699205156441794340321594716851470397814505922113374740460562","seed":107620229815429275699205156441794340321594716851470397814505922113374740460562,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3040.336696 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3040.336696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.112054289017742277337407683449916021999553889761278765420651762325477362099064","seed":112054289017742277337407683449916021999553889761278765420651762325477362099064,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 2550.033296 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2550.033296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"39.chip_sw_all_escalation_resets.62431161741440791140777489781604266445882565233790221835697602370410724860949","seed":62431161741440791140777489781604266445882565233790221835697602370410724860949,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3476.055156 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3476.055156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"65.chip_sw_all_escalation_resets.55933026815044351785289620827810294887747334787154231469927711204336076487294","seed":55933026815044351785289620827810294887747334787154231469927711204336076487294,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2821.750184 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2821.750184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.28403367545365077346968018371253077222686420273242350880629465179607585089213","seed":28403367545365077346968018371253077222686420273242350880629465179607585089213,"line":287,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.52692727227768876848429047660966398720612705798190208475943241908512748580192","seed":52692727227768876848429047660966398720612705798190208475943241908512748580192,"line":374,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 10281.227951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.37906202126464712359889142142795029668990918615077210953215757320225054636486","seed":37906202126464712359889142142795029668990918615077210953215757320225054636486,"line":374,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 9428.483760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.44363131526861533296460202753449922955411097193554885908879426922298997720601","seed":44363131526861533296460202753449922955411097193554885908879426922298997720601,"line":346,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 5669.509145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.85436476603484712271474763233583330970303130321680049513628366078235906985471","seed":85436476603484712271474763233583330970303130321680049513628366078235906985471,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 10714.876224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.83008795405396800043567982093655068617907629024954898908469862177477986937186","seed":83008795405396800043567982093655068617907629024954898908469862177477986937186,"line":341,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 6600.060775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.103425383442265933809035398558384171963114445803211670387806366882067243900801","seed":103425383442265933809035398558384171963114445803211670387806366882067243900801,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 11663.694358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.77480343185406779422297853087045273353778865960352196695850936693336325149000","seed":77480343185406779422297853087045273353778865960352196695850936693336325149000,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 10687.209454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.50462138259361046695441195785567604326098295519609487037637600403358490766871","seed":50462138259361046695441195785567604326098295519609487037637600403358490766871,"line":341,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 5306.276235 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError!":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.49078874777546337224984307793147487108423916942284183987253167409677738287353","seed":49078874777546337224984307793147487108423916942284183987253167409677738287353,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 25751.456615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.105208795522650044624907050816038293747345337590425742271386742948249601455548","seed":105208795522650044624907050816038293747345337590425742271386742948249601455548,"line":303,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2033.427734 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2033.427734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.63763107671574170157724617402547545885451768262314268620458852688320330905652","seed":63763107671574170157724617402547545885451768262314268620458852688320330905652,"line":322,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 6393.799928 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 6393.799928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.90810262040875007097418116443093822485338478571853321282715805427281461703700","seed":90810262040875007097418116443093822485338478571853321282715805427281461703700,"line":303,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2191.890813 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2191.890813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.36490403673476547436741808708257856626359531583927393623507214823575888501534","seed":36490403673476547436741808708257856626359531583927393623507214823575888501534,"line":344,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 13192.432000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 13192.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.62178514490972172195316922847520281659369542746045731920031973657204895347343","seed":62178514490972172195316922847520281659369542746045731920031973657204895347343,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7837.556000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7837.556000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.56192186568518231772023221400235648597466067830195931575202297720603631954937","seed":56192186568518231772023221400235648597466067830195931575202297720603631954937,"line":344,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 14209.800000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 14209.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.84451418785979401667006828189232942693885480389205755340039890202077492154406","seed":84451418785979401667006828189232942693885480389205755340039890202077492154406,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10364.439500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10364.439500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.112722629564899280610964505348294595914292703449699577044160602814338917720725","seed":112722629564899280610964505348294595914292703449699577044160602814338917720725,"line":325,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7839.333500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7839.333500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.7527232865368890903355003809831856014571673413465219177829343307831795026315","seed":7527232865368890903355003809831856014571673413465219177829343307831795026315,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8200.554000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8200.554000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_por_reset.67841702413906554519580123953823392191977024054715567878675675365630168381655","seed":67841702413906554519580123953823392191977024054715567878675675365630168381655,"line":325,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7131.013000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7131.013000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.59965666411639960976354330579996884272654868627390661908870144482768001109193","seed":59965666411639960976354330579996884272654868627390661908870144482768001109193,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8043.700000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8043.700000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.60948377317094211802741283482424619969717522927163440088652983821123965557836","seed":60948377317094211802741283482424619969717522927163440088652983821123965557836,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3192.563315 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3192.563315 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.73386118675987340556917506699842584209965607846404772420425506696616770651960","seed":73386118675987340556917506699842584209965607846404772420425506696616770651960,"line":329,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 6658.821208 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 6658.821208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.41907689071813305379506056402553462642007834527994308633115006151853816545023","seed":41907689071813305379506056402553462642007834527994308633115006151853816545023,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3225.023608 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3225.023608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.58258865147254039046196632411621670913006153920251732218497322533280171108343","seed":58258865147254039046196632411621670913006153920251732218497322533280171108343,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3188.258701 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3188.258701 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.100181116588005682800609729721052961484968513750126202862013774880797734801674","seed":100181116588005682800609729721052961484968513750126202862013774880797734801674,"line":378,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 21313.562600 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 21313.562600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.62077479372467564869693068088349469407317631139231381372773235312039870790910","seed":62077479372467564869693068088349469407317631139231381372773235312039870790910,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.75569118006749684052502929143283758294667912438663052278318302037224010933748","seed":75569118006749684052502929143283758294667912438663052278318302037224010933748,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.106542251248201919913408878188802635350003168000145307163750833831081213074988","seed":106542251248201919913408878188802635350003168000145307163750833831081213074988,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.67950425852616910325264863793394244407852158904766978117332771719890483236147","seed":67950425852616910325264863793394244407852158904766978117332771719890483236147,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.76126290602174869428536358313272766382340034283370125720652261793150681441743","seed":76126290602174869428536358313272766382340034283370125720652261793150681441743,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.25914109265897528216660788684106327500166287834300665219368481260186487906708","seed":25914109265897528216660788684106327500166287834300665219368481260186487906708,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.79457875901224500428064027490278637563480019245652351358752357699386293591486","seed":79457875901224500428064027490278637563480019245652351358752357699386293591486,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.86671959267873775172273085285339238581553534209653608992573301424034964349326","seed":86671959267873775172273085285339238581553534209653608992573301424034964349326,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.15368811474157671129094508107128059587507597275933280288181412797971368589696","seed":15368811474157671129094508107128059587507597275933280288181412797971368589696,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.100798980333739219725016274454634723625393027238144004177696739244692591719560","seed":100798980333739219725016274454634723625393027238144004177696739244692591719560,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.58991241111806109042073962689897867972571151757588675037956824453151307575059","seed":58991241111806109042073962689897867972571151757588675037956824453151307575059,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.105245153570031846716300332981514127913309382840180699575851544485039783101398","seed":105245153570031846716300332981514127913309382840180699575851544485039783101398,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"2.chip_sw_csrng_edn_concurrency_reduced_freq.21072752569256287772638912117129448282078877265582168087880184712543111334683","seed":21072752569256287772638912117129448282078877265582168087880184712543111334683,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.99443850174558928190154490692389682288241851809805468133734919466118235976700","seed":99443850174558928190154490692389682288241851809805468133734919466118235976700,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.100935712415468465918201145146530346894327439193743338218304062596977397324029","seed":100935712415468465918201145146530346894327439193743338218304062596977397324029,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2595.013760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.96626244751365986010527291678916494605970926992821946229062114629099692707894","seed":96626244751365986010527291678916494605970926992821946229062114629099692707894,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2157.567987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.78442627463129643711993946988955316726551331900151214477255150420917474939505","seed":78442627463129643711993946988955316726551331900151214477255150420917474939505,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3200.236985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.51970132049448039398261808256226622628112749979782107364893693705951097699464","seed":51970132049448039398261808256226622628112749979782107364893693705951097699464,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2729.335804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.103329310270959080132513487074034746498382132920776057225721369149551976231179","seed":103329310270959080132513487074034746498382132920776057225721369149551976231179,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3468.056412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.113702977233533134392464741808731344504628951643842867425055911102735580722658","seed":113702977233533134392464741808731344504628951643842867425055911102735580722658,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3530.604946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.57429285052006745904824341250776332943143178619476076020115439839352906628727","seed":57429285052006745904824341250776332943143178619476076020115439839352906628727,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2748.453599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.98089647746879862726454491084936921699538935108259916278979526017099383879884","seed":98089647746879862726454491084936921699538935108259916278979526017099383879884,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2799.133672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.74799250690161236724381993425525010191240187025716598329902298965788160258590","seed":74799250690161236724381993425525010191240187025716598329902298965788160258590,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3160.913785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.110962065519372016361483051692383922016816916443419104133404262065976866483276","seed":110962065519372016361483051692383922016816916443419104133404262065976866483276,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2730.553824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.66829873284186692982644209685959675664707486315832960517880720686735064134862","seed":66829873284186692982644209685959675664707486315832960517880720686735064134862,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2429.487300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.18127608006640654598763194588910113518246037686577741059521348077366470759614","seed":18127608006640654598763194588910113518246037686577741059521348077366470759614,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2354.760640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.93504694034485450356429118810934024042894995863201892602292490385478545845518","seed":93504694034485450356429118810934024042894995863201892602292490385478545845518,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3141.503424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.109282046190598937824408123941109906724378031401241980723057453587224594409716","seed":109282046190598937824408123941109906724378031401241980723057453587224594409716,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2729.379542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.65775212083755039331132789168123437006694116381917558080724434547622791737163","seed":65775212083755039331132789168123437006694116381917558080724434547622791737163,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2908.895596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.81940976174961357260016595867617277428739311522080357622071818648924851308557","seed":81940976174961357260016595867617277428739311522080357622071818648924851308557,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3194.908953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.13735582919277391292333736841755903527681069024383628319112107559095395449738","seed":13735582919277391292333736841755903527681069024383628319112107559095395449738,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2831.101336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.58724398105734959402487498819127754551199317251647156171286145548443274563225","seed":58724398105734959402487498819127754551199317251647156171286145548443274563225,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3010.187276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.106448129053485821794174098690858877237320694165646554270290259414248817225064","seed":106448129053485821794174098690858877237320694165646554270290259414248817225064,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2769.124656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.54452002232474686315718835719094891011962849424531453357434440133652899059783","seed":54452002232474686315718835719094891011962849424531453357434440133652899059783,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3533.681620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.18481225473782182893194667776592026306343684938883424929584307184800193335316","seed":18481225473782182893194667776592026306343684938883424929584307184800193335316,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2302.551360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.21145933348802051580204562140463548738228014272342597872356443761009046337071","seed":21145933348802051580204562140463548738228014272342597872356443761009046337071,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2475.420540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.42068548888618592705082512194774720618491151682131842316476137840815103371751","seed":42068548888618592705082512194774720618491151682131842316476137840815103371751,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3611.849370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.41719169398575827618572712441283911166393031267118916042711718576428175564959","seed":41719169398575827618572712441283911166393031267118916042711718576428175564959,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2604.093967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.40523727771080717816334574248024746509923860793647277128972747459250991335587","seed":40523727771080717816334574248024746509923860793647277128972747459250991335587,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2857.907100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.81892263084401267776176549215357506341140119379222016310232257880612456136765","seed":81892263084401267776176549215357506341140119379222016310232257880612456136765,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3006.039780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.26912171804979021714341536712027829329168999502760247164126710444768267620503","seed":26912171804979021714341536712027829329168999502760247164126710444768267620503,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3031.342883 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.8284677236569513365425703891470048420634030068499060136580694181264316082229","seed":8284677236569513365425703891470048420634030068499060136580694181264316082229,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2845.951674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.14636709472690042276782746947460169448293933334040695800921961659427613511110","seed":14636709472690042276782746947460169448293933334040695800921961659427613511110,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2966.354888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.107369648920770629037969947939394736174728705835313065857711916212552183241077","seed":107369648920770629037969947939394736174728705835313065857711916212552183241077,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2555.732407 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1845476058765396695526254130886738473163546734067765560619195252365410429091","seed":1845476058765396695526254130886738473163546734067765560619195252365410429091,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3525.538031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.95711898201678429701767789745905399954015120608982517987021075363201895420870","seed":95711898201678429701767789745905399954015120608982517987021075363201895420870,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2642.332330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.36227526100389214156686170666169920631982150733861820011179347365562555903558","seed":36227526100389214156686170666169920631982150733861820011179347365562555903558,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2855.951516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.83435655375245131817725777648744805937323079632222311346928150672414564552265","seed":83435655375245131817725777648744805937323079632222311346928150672414564552265,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2664.714440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.98782892567944444961729666446873611922978168833727361856529339685573488878940","seed":98782892567944444961729666446873611922978168833727361856529339685573488878940,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2835.419981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.79891750183441198052388905719601290790623423976686005831073974972983015433028","seed":79891750183441198052388905719601290790623423976686005831073974972983015433028,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2726.238688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.35935912839823451754050440015919162500742222534527050474695598846364078652851","seed":35935912839823451754050440015919162500742222534527050474695598846364078652851,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2353.186088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339127195215953750877356220556112298051664773236121431365503701348617711406","seed":2339127195215953750877356220556112298051664773236121431365503701348617711406,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3477.876620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.95043876897149260247808381951620092001132468994467555870862460968685807985353","seed":95043876897149260247808381951620092001132468994467555870862460968685807985353,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2703.108504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.100054292536246310809119352151431264243295137800874114066588683620153813723094","seed":100054292536246310809119352151431264243295137800874114066588683620153813723094,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2681.249820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.29193272835618228444184135524744579596537691363627924037994635047498901380978","seed":29193272835618228444184135524744579596537691363627924037994635047498901380978,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2899.667005 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.35871645612702004931544227708227676580636851295215156013703335386104334995070","seed":35871645612702004931544227708227676580636851295215156013703335386104334995070,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2782.160524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.92176609581752700594600801968661466894824016771953165210942745559992257853531","seed":92176609581752700594600801968661466894824016771953165210942745559992257853531,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3283.746593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.5328462255931943126659284701785784847563996598438524435382989419228709220056","seed":5328462255931943126659284701785784847563996598438524435382989419228709220056,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2885.903640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.53869354116789836710319758745884709851223872872634532231522850608221803584843","seed":53869354116789836710319758745884709851223872872634532231522850608221803584843,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2733.168835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.73425203265764681772948309964857998151516369748183537199089349143218544626300","seed":73425203265764681772948309964857998151516369748183537199089349143218544626300,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2735.560567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.37955773129549825535403478155636928265082231324240809049918947052644298622060","seed":37955773129549825535403478155636928265082231324240809049918947052644298622060,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3678.836542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.46620710676226526354329845175538201309489181736034940240384765160528407475011","seed":46620710676226526354329845175538201309489181736034940240384765160528407475011,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3049.933809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.76035204572125198268322220350250239086321270081857748179296280361555091215449","seed":76035204572125198268322220350250239086321270081857748179296280361555091215449,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2378.234965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.82384088213183229402990280206237853089282068348344378273127086676549609172403","seed":82384088213183229402990280206237853089282068348344378273127086676549609172403,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3280.492302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867029237621798235833732611809448890399826295006264544864696126419049801236","seed":2867029237621798235833732611809448890399826295006264544864696126419049801236,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3443.632200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.41243132572968168418898191007813606888328567476277203997355628584644223204007","seed":41243132572968168418898191007813606888328567476277203997355628584644223204007,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2430.075782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.881999670107252537684805035399337865588331704709515867483664486358874540803","seed":881999670107252537684805035399337865588331704709515867483664486358874540803,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2803.924739 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.111379335567924837231307071222366918541003220713110451849254925082801032668381","seed":111379335567924837231307071222366918541003220713110451849254925082801032668381,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2891.610474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.74459698474083505516840181752331801008119899590123728108439556442633162980730","seed":74459698474083505516840181752331801008119899590123728108439556442633162980730,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3451.860358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.92047586428776377455282801311304816185292613747117155949601689645177849389434","seed":92047586428776377455282801311304816185292613747117155949601689645177849389434,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2676.105724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.105091078862557584948315003953040511425374358436453702242325307920722377695201","seed":105091078862557584948315003953040511425374358436453702242325307920722377695201,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3233.762760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.15851182603356509150667403451059127914056241558451911621471697569203419662140","seed":15851182603356509150667403451059127914056241558451911621471697569203419662140,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2350.945677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.74942819455476321174403773115992414355515092525888926809258926852787864520996","seed":74942819455476321174403773115992414355515092525888926809258926852787864520996,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2596.307804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.33932129383497463407897663182959693727763746718425165239884825024024911656234","seed":33932129383497463407897663182959693727763746718425165239884825024024911656234,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3354.565000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.11714754210574115340632501792456932522551407131266267049330041616471903218465","seed":11714754210574115340632501792456932522551407131266267049330041616471903218465,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3039.623780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.55655144871344223084041943756125429040813949485859221712667874913433813396021","seed":55655144871344223084041943756125429040813949485859221712667874913433813396021,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2465.986174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.57842874912425715993539032626519159819262600527904407263535209008834201596164","seed":57842874912425715993539032626519159819262600527904407263535209008834201596164,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3090.913640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.113656550821680472171814816682167439842401006617818351347269694598662491947558","seed":113656550821680472171814816682167439842401006617818351347269694598662491947558,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2844.348850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.101282900225380103369066473341629487911304845907964945001048664360188217588143","seed":101282900225380103369066473341629487911304845907964945001048664360188217588143,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3199.760006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.42480869823399054758672108495967394394702040987011086084955718121621769886276","seed":42480869823399054758672108495967394394702040987011086084955718121621769886276,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3728.305623 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.111376140186051687546554181635340457280164049632950512261979476372191759464305","seed":111376140186051687546554181635340457280164049632950512261979476372191759464305,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3524.280003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.46686768802587711861329196075712412723672459599711536130481997225639276198489","seed":46686768802587711861329196075712412723672459599711536130481997225639276198489,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3448.657625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.92913225160674609496264247825838050937655040578000228785272225072854429844063","seed":92913225160674609496264247825838050937655040578000228785272225072854429844063,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2899.230984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.109547809412506004208642016194072835763506613701171853878328337995077520922432","seed":109547809412506004208642016194072835763506613701171853878328337995077520922432,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2494.188100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.13129365152572983763205563677760815111502282664934744509190703320224950777604","seed":13129365152572983763205563677760815111502282664934744509190703320224950777604,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2848.945475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.80500733592845893898722303048317653652093799852216755865335067708240917153801","seed":80500733592845893898722303048317653652093799852216755865335067708240917153801,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3178.535228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.29640561450954760041183632133162527414132296891102926494840024261782659057477","seed":29640561450954760041183632133162527414132296891102926494840024261782659057477,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3097.150070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.96018384578027806350789059882585350098952991572962303999673142781305566629359","seed":96018384578027806350789059882585350098952991572962303999673142781305566629359,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2723.208784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.37970999974659942099887371739177344079414084001630713628522063461761610081153","seed":37970999974659942099887371739177344079414084001630713628522063461761610081153,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2978.348076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.102882257298202410800548537571332373611989004132850759787694520215309905911424","seed":102882257298202410800548537571332373611989004132850759787694520215309905911424,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2256.996264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.38233484432437375307633675162020084397627260321954181878035846010525856508245","seed":38233484432437375307633675162020084397627260321954181878035846010525856508245,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2644.304065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.28566462455435389889204268346784768306919386437619282672752119720132292826373","seed":28566462455435389889204268346784768306919386437619282672752119720132292826373,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3278.131352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.12057266433557579785430429502513324774966822169443520869799638580117510195194","seed":12057266433557579785430429502513324774966822169443520869799638580117510195194,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3044.897370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.77748973732088496081636265252019494536257512958446708501198327464326432445446","seed":77748973732088496081636265252019494536257512958446708501198327464326432445446,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3216.162600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.68504127234721706865595185457831052494019458406971350125104738143040291823936","seed":68504127234721706865595185457831052494019458406971350125104738143040291823936,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2916.697752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.64177751753973459520469183511369460027864449188098274323579510103436002831646","seed":64177751753973459520469183511369460027864449188098274323579510103436002831646,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3298.069962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.15596356075512524417604099290408629725172094091621927645180358394517031292345","seed":15596356075512524417604099290408629725172094091621927645180358394517031292345,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2422.577185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.84201271566998846518913967759640171360682572932294931354092948151123618801283","seed":84201271566998846518913967759640171360682572932294931354092948151123618801283,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2588.179542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398893734017530986752037420068951452225948213249961980476749218061673326794","seed":2398893734017530986752037420068951452225948213249961980476749218061673326794,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2770.098777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.43813869577341458596912375970293270334642417627961621321609958479757596071034","seed":43813869577341458596912375970293270334642417627961621321609958479757596071034,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2845.120000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.43768284626708035885433980112709850216350084685852387343540229392641154402926","seed":43768284626708035885433980112709850216350084685852387343540229392641154402926,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3246.290358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.39204966219971077475609314743231952208236555968447343412217093973222054425058","seed":39204966219971077475609314743231952208236555968447343412217093973222054425058,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3293.108723 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.84936294538483835367395943119388985809868592759884913210370447719102909562651","seed":84936294538483835367395943119388985809868592759884913210370447719102909562651,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3367.042184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.79490916799796681304115038949180784477601940402687077636080279742698408672440","seed":79490916799796681304115038949180784477601940402687077636080279742698408672440,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3195.429504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.95609456959104686949714553368363219007226631630699511605445671084586551188512","seed":95609456959104686949714553368363219007226631630699511605445671084586551188512,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3227.322116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(reset_cause == HwReq)'":[{"name":"chip_sw_sensor_ctrl_alert","qual_name":"0.chip_sw_sensor_ctrl_alert.62285761194825308803372775972334818399247957626846712153578208888162482414381","seed":62285761194825308803372775972334818399247957626846712153578208888162482414381,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest/run.log","log_context":["UVM_ERROR @ 3083.970320 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A\n","UVM_INFO @ 3083.970320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sensor_ctrl_alert","qual_name":"3.chip_sw_sensor_ctrl_alert.56006812332716503625286368473882872613337955013276023447309966419999985258172","seed":56006812332716503625286368473882872613337955013276023447309966419999985258172,"line":346,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest/run.log","log_context":["UVM_ERROR @ 7058.131988 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A\n","UVM_INFO @ 7058.131988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.790939460204577529815017002152467097404658421769761726276002081597642101017","seed":790939460204577529815017002152467097404658421769761726276002081597642101017,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32616) { a_addr: 'h10684  a_data: 'hfef96fd6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1a2c6  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2821.850934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.87067322124670259733423819251020429145569657188203608975182676863610005270139","seed":87067322124670259733423819251020429145569657188203608975182676863610005270139,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32280) { a_addr: 'h105a8  a_data: 'hc0145723  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1ae58  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2314.414798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.105860091288370611891658548684192315375551663448818626968371235341885948567782","seed":105860091288370611891658548684192315375551663448818626968371235341885948567782,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34324) { a_addr: 'h10678  a_data: 'h9284b612  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h19eee  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2393.800782 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.33249401685588575590812246822688373281226765154938879370029413709920293130214","seed":33249401685588575590812246822688373281226765154938879370029413709920293130214,"line":224,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31516) { a_addr: 'h10578  a_data: 'h2004358f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1929e  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2609.395339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.16945404322112221212962977496851788892161120803669605076543755923177249240479","seed":16945404322112221212962977496851788892161120803669605076543755923177249240479,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31538) { a_addr: 'h1055c  a_data: 'ha638697d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h186f7  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2213.176490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.109378983361804318393732104313765390066774498342126375884160750538441681992922","seed":109378983361804318393732104313765390066774498342126375884160750538441681992922,"line":224,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32106) { a_addr: 'h10698  a_data: 'h89a6a36c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h19e05  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2453.835736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.79794208458241284796388714197005933333598550774495392596233067843190298864656","seed":79794208458241284796388714197005933333598550774495392596233067843190298864656,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32172) { a_addr: 'h105d0  a_data: 'h92eaea8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1ae66  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2833.692982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.6069344099695525714622209309400747168899833171704764111018174645812644690133","seed":6069344099695525714622209309400747168899833171704764111018174645812644690133,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33554) { a_addr: 'h104dc  a_data: 'h1e1de89b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h1b117  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2112.351438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.2371350532285033719703454125197199394683305447105551157371723473539561519838","seed":2371350532285033719703454125197199394683305447105551157371723473539561519838,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34734) { a_addr: 'h1035c  a_data: 'hb5eab8a9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h19eeb  d_param: 'h0  d_source: 'h3a  d_data: 'h100073  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd04  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2917.046071 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.76972428975011452395508007381678163620594480475147152462932959025147597409384","seed":76972428975011452395508007381678163620594480475147152462932959025147597409384,"line":218,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@50346) { a_addr: 'h106ec  a_data: 'h686ea862  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h18651  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2664.480500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.45543946199520754347680718845138208475554278124263637348924673903477171696238","seed":45543946199520754347680718845138208475554278124263637348924673903477171696238,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@42148) { a_addr: 'h10100  a_data: 'h5a5aca07  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h181ea  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2423.985410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.114062982204039102194934409673289821776781472239722825246722587646689008845822","seed":114062982204039102194934409673289821776781472239722825246722587646689008845822,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36348) { a_addr: 'h107bc  a_data: 'hefd29c3e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h18d2a  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3016.338912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.66568596665587497457576620279110819438751737338181008816565438869456928190385","seed":66568596665587497457576620279110819438751737338181008816565438869456928190385,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@43300) { a_addr: 'h10674  a_data: 'h93d75c14  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h186bd  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1965.469880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.23781458541454136114337826581178868554480483256689956858667465779242612451648","seed":23781458541454136114337826581178868554480483256689956858667465779242612451648,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31590) { a_addr: 'h1049c  a_data: 'h659738bc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h199a7  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2387.748580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.12944138557908087938152360330460206727578708832810640382149946609179174809158","seed":12944138557908087938152360330460206727578708832810640382149946609179174809158,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36686) { a_addr: 'h105d8  a_data: 'h9113d7a4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h1bafd  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2387.883144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.28769536957092596706714499103084203967604306438067159057633786705640637013514","seed":28769536957092596706714499103084203967604306438067159057633786705640637013514,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33520) { a_addr: 'h1068c  a_data: 'h92e26a7c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h4  a_user: 'h1b67a  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2076.289046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.111905917398894083856562008217694857379546249458080139547472542382829094096533","seed":111905917398894083856562008217694857379546249458080139547472542382829094096533,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@39136) { a_addr: 'h106b0  a_data: 'hd96a51c5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1925b  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2644.349808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.108642979032110768127288903224099999752179222792254664433435639995453703263820","seed":108642979032110768127288903224099999752179222792254664433435639995453703263820,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31782) { a_addr: 'h10464  a_data: 'hd8a22c5c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1a961  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2775.042844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.25926318642822566013542950070394448208678308623837432722552774710316877492711","seed":25926318642822566013542950070394448208678308623837432722552774710316877492711,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33072) { a_addr: 'h1074c  a_data: 'hbcd6e916  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1a949  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2060.284310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.114256186749200503828288077705534523830016377267244724508741710225846026490603","seed":114256186749200503828288077705534523830016377267244724508741710225846026490603,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33026) { a_addr: 'h107b0  a_data: 'hcce55442  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h19554  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2239.134776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.51449819855131467234041554734091049807833386959668320764903377923307261411146","seed":51449819855131467234041554734091049807833386959668320764903377923307261411146,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32494) { a_addr: 'h106ac  a_data: 'h4f96ddb1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h1aefd  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2541.134928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.106289773604428075867111110585494010652818687633763948488559979592714378103805","seed":106289773604428075867111110585494010652818687633763948488559979592714378103805,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35296) { a_addr: 'h10660  a_data: 'hf80a081b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1aeac  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2440.103752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.62783269662862798266905995186860981703443573799799046243951007971774367281451","seed":62783269662862798266905995186860981703443573799799046243951007971774367281451,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33106) { a_addr: 'h104e8  a_data: 'h4d11b47c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h4  a_user: 'h181d5  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2404.635425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.80854003851797464390879271304366399903017956401789883390307084016830624578289","seed":80854003851797464390879271304366399903017956401789883390307084016830624578289,"line":218,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@184076) { a_addr: 'h1064c  a_data: 'h6d7f8eaf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h1ae6e  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 4011.693528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.34953048462908609114627307967859620116200760616743659573363992576323778799758","seed":34953048462908609114627307967859620116200760616743659573363992576323778799758,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32464) { a_addr: 'h10374  a_data: 'he4010062  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h19293  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1990.355000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.47893441282308116511971835043548276333382679459765067869888224952841934318217","seed":47893441282308116511971835043548276333382679459765067869888224952841934318217,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32362) { a_addr: 'h10468  a_data: 'hc3d26c29  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h4  a_user: 'h1b17b  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2398.564244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.96769282442128366879602440127256905086469662638672084262554546115889181256594","seed":96769282442128366879602440127256905086469662638672084262554546115889181256594,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32334) { a_addr: 'h10780  a_data: 'he044c5e9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1a92f  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2789.601625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.5935626800814929889929086518188704788658352307880555844420135763485765200970","seed":5935626800814929889929086518188704788658352307880555844420135763485765200970,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32482) { a_addr: 'h106d0  a_data: 'h713abd59  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h1a26d  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2274.658332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.27363896271368965472484205587569111858382167537694739980600608393558479054732","seed":27363896271368965472484205587569111858382167537694739980600608393558479054732,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3566.420205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.57007270721560775328138326458856297676984669426067088869760696794584903761470","seed":57007270721560775328138326458856297676984669426067088869760696794584903761470,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3192.808529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.107920766171808093014136919818724791450894882059170876858305351062105817827086","seed":107920766171808093014136919818724791450894882059170876858305351062105817827086,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3242.814705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.38418304992860177808036542026221447951263738365308778353249320821057429480489","seed":38418304992860177808036542026221447951263738365308778353249320821057429480489,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3075400) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.39489911335712688699173603081862472569904035572584431086910425673213347792338","seed":39489911335712688699173603081862472569904035572584431086910425673213347792338,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=267874) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=289515) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=267069) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.7734113682202076627112346165688305761454115508493682718279612059434461560373","seed":7734113682202076627112346165688305761454115508493682718279612059434461560373,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.37295145740612807185429196828536602319460647036904408133307754778994158892649","seed":37295145740612807185429196828536602319460647036904408133307754778994158892649,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.95354315887827040310583946839182506798782007792621186926638540062015400765064","seed":95354315887827040310583946839182506798782007792621186926638540062015400765064,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.44941736032012691139957162573576849062209688089603313541943225835730333042531","seed":44941736032012691139957162573576849062209688089603313541943225835730333042531,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.55701579164580563425866728984094595970481585094459168566880458429986998572239","seed":55701579164580563425866728984094595970481585094459168566880458429986998572239,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=264738) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=264860) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.63885800150808221145562724768027463784641198396336665672668911840366065221442","seed":63885800150808221145562724768027463784641198396336665672668911840366065221442,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=402862) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.70167953735598940326287070491834295846224097974995901979554484222309034986007","seed":70167953735598940326287070491834295846224097974995901979554484222309034986007,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.67508153870079275315802751622394010947596263098884444228122957301143238683587","seed":67508153870079275315802751622394010947596263098884444228122957301143238683587,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.113300479030584305643060260626271526369695757980708698546867541988146313944245","seed":113300479030584305643060260626271526369695757980708698546867541988146313944245,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.11146861492460145877241767834299818124741576868298445347973141504804151965714","seed":11146861492460145877241767834299818124741576868298445347973141504804151965714,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.81474070664635187454734196471170634360064210440626689774852904780773047794552","seed":81474070664635187454734196471170634360064210440626689774852904780773047794552,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.79609385420880341160476370776421701522705162675968430550697937319492423019635","seed":79609385420880341160476370776421701522705162675968430550697937319492423019635,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.104640314287898178328902485460956663320544493631358881129856906214655643366280","seed":104640314287898178328902485460956663320544493631358881129856906214655643366280,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.19798345278570202577547600333069381823255784218710265638733381176539048612468","seed":19798345278570202577547600333069381823255784218710265638733381176539048612468,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.84058271948219249169680956901833477610701662785049572092689628558351845287056","seed":84058271948219249169680956901833477610701662785049572092689628558351845287056,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.11433841426729467552794027333724145581486513326544846765254592894432795667653","seed":11433841426729467552794027333724145581486513326544846765254592894432795667653,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.110404732499445621492062814721586727709879826355723161742132888296419579223048","seed":110404732499445621492062814721586727709879826355723161742132888296419579223048,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.71593482260619704152438398662286792346531945126994329523925370968766854411576","seed":71593482260619704152438398662286792346531945126994329523925370968766854411576,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.33320369036392073021283875686487218311047306896772956394833534182833254660590","seed":33320369036392073021283875686487218311047306896772956394833534182833254660590,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.73651511538300333437681517277467131765186526856570453035529679889402211780735","seed":73651511538300333437681517277467131765186526856570453035529679889402211780735,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.47546611198338458378707874076210193364532705303679283342997939073194888987322","seed":47546611198338458378707874076210193364532705303679283342997939073194888987322,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.28159491338919821735705671944723715930622134239992773500512115149193315193797","seed":28159491338919821735705671944723715930622134239992773500512115149193315193797,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.86897084225810517922070316246564004242921082585575003947832987973536828524621","seed":86897084225810517922070316246564004242921082585575003947832987973536828524621,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.31352850277230977471518291103257282926493126305320489435525501931078067743219","seed":31352850277230977471518291103257282926493126305320489435525501931078067743219,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.52796265379645270434141374813932982906765915802300626444494921652080531270461","seed":52796265379645270434141374813932982906765915802300626444494921652080531270461,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.31580581556169363465660987295607712756924058081563083514226516375020307515650","seed":31580581556169363465660987295607712756924058081563083514226516375020307515650,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.53559103017690790740356247224882857298144920155107612939978416092344914580992","seed":53559103017690790740356247224882857298144920155107612939978416092344914580992,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.66947743530078997816242540996138525254709304197096315534014018846686225157446","seed":66947743530078997816242540996138525254709304197096315534014018846686225157446,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.97853684273139734492560168999734917453244482415304769433095562774269964858008","seed":97853684273139734492560168999734917453244482415304769433095562774269964858008,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.39175242545863909385582332262950095000753536840721404060446489400785290450620","seed":39175242545863909385582332262950095000753536840721404060446489400785290450620,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=267874) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=289515) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=267069) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.73260142715666915929989529442659018460254548327878883956403676466908364225933","seed":73260142715666915929989529442659018460254548327878883956403676466908364225933,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["Another command (pid=367052) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=369054) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=355701) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.110020973800889648738342634731297460462394583406985507832388888066612622781979","seed":110020973800889648738342634731297460462394583406985507832388888066612622781979,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["Another command (pid=380243) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=345635) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=340855) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.21274024285527415088575247125272641852473014744302925551776369072723229939620","seed":21274024285527415088575247125272641852473014744302925551776369072723229939620,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=340855) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=329430) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.95350808888519975698998215950668039940250160957826646370235630561380425960199","seed":95350808888519975698998215950668039940250160957826646370235630561380425960199,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["Another command (pid=390883) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=394534) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=394821) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.94485350606373985286464050054556909026472582993052890864391780176858933403438","seed":94485350606373985286464050054556909026472582993052890864391780176858933403438,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.85421458219020594884641227511246357600340268340961205393668484480602285837958","seed":85421458219020594884641227511246357600340268340961205393668484480602285837958,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.47382425675137655692806336115817597917921852395192127151551028554883700823883","seed":47382425675137655692806336115817597917921852395192127151551028554883700823883,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.5825475373662309429176486136338309282181166113960833100688057962476082390653","seed":5825475373662309429176486136338309282181166113960833100688057962476082390653,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=298800) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=303397) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=300557) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.13158765290745270571988749545365378735163534706753887996082588987373278067170","seed":13158765290745270571988749545365378735163534706753887996082588987373278067170,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=289515) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=267069) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=291171) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.82440630375546052017060545967260603189624248105775053252063826718863995173421","seed":82440630375546052017060545967260603189624248105775053252063826718863995173421,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=264738) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=264860) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.110910819142898572149150187827871464466829867345541281232867780422392203401372","seed":110910819142898572149150187827871464466829867345541281232867780422392203401372,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3993615) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.19665824922912016540919418750955143485823655086689753271267544437233684241137","seed":19665824922912016540919418750955143485823655086689753271267544437233684241137,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=288626) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=269715) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=291383) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.55056789322856117166616027237440683801908484229961141757790269521781468087472","seed":55056789322856117166616027237440683801908484229961141757790269521781468087472,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.68997776038925905181573279212859434638240783640111039877995947410979747704332","seed":68997776038925905181573279212859434638240783640111039877995947410979747704332,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.69927409772616133680212456285372519421993087857743492524090553692323428487958","seed":69927409772616133680212456285372519421993087857743492524090553692323428487958,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.8932368455768565733697891309813997672846253077062432208349435916554616979552","seed":8932368455768565733697891309813997672846253077062432208349435916554616979552,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.115092747809710835170882892223124728111757688838881910037288837606680241554703","seed":115092747809710835170882892223124728111757688838881910037288837606680241554703,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=269715) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=291383) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=272789) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.28771507313883209699772282443102483840082740370659846528138008439209398820360","seed":28771507313883209699772282443102483840082740370659846528138008439209398820360,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=270116) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=267714) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.97307642215681643051391017425125764203381547190154563525061281420098529653994","seed":97307642215681643051391017425125764203381547190154563525061281420098529653994,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=267528) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=288626) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=269715) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.49021958083531261630550525128315869284252777654917624428075554810225678384125","seed":49021958083531261630550525128315869284252777654917624428075554810225678384125,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.59613315217822812194552217749599611404407170680201192818066039178239801151372","seed":59613315217822812194552217749599611404407170680201192818066039178239801151372,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=305577) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=268316) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=306141) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.75673912448643095666999661884026407758353231059683857881055429702563284333120","seed":75673912448643095666999661884026407758353231059683857881055429702563284333120,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.33735374790096893825062644316633503475355755232485327152014048909030577757177","seed":33735374790096893825062644316633503475355755232485327152014048909030577757177,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.108776663284040550762630413133104379295863391137651694769693662568695730934463","seed":108776663284040550762630413133104379295863391137651694769693662568695730934463,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.90573091770280871987822103904528045505995805886301468977453699202215824438644","seed":90573091770280871987822103904528045505995805886301468977453699202215824438644,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.53997618709515300996964992314892051371420823584460986449384207335719369281985","seed":53997618709515300996964992314892051371420823584460986449384207335719369281985,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=314646) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=316393) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=320541) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.36776349778568643763411472878482651544789487829229073241444643315392530050689","seed":36776349778568643763411472878482651544789487829229073241444643315392530050689,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=295185) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=281470) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=265314) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.87412013920334527719436365420448994752859164530409470492218045827848935734207","seed":87412013920334527719436365420448994752859164530409470492218045827848935734207,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=289515) is running. Waiting for it to complete on the server (server_pid=264745)...\n","Another command (pid=267069) is running. Waiting for it to complete on the server (server_pid=264745)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.60723876112512409074177307425342705317136776429390137392014098860776922578945","seed":60723876112512409074177307425342705317136776429390137392014098860776922578945,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.86418670067890016326544462988789927235346743810998851091626065491484665672451","seed":86418670067890016326544462988789927235346743810998851091626065491484665672451,"line":357,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.65834605903447055741592101329369156343285185025403833560287247136874840317532","seed":65834605903447055741592101329369156343285185025403833560287247136874840317532,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.10763487177618331643650931820281597225760274519110101627323682278277565132154","seed":10763487177618331643650931820281597225760274519110101627323682278277565132154,"line":352,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.51479486811299196381231328569717058085367766930719421261398426268358675855558","seed":51479486811299196381231328569717058085367766930719421261398426268358675855558,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.65230062614899832418612786320172932979574550619238985351100852667133775563918","seed":65230062614899832418612786320172932979574550619238985351100852667133775563918,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.1903422557619808550262567587939255293989520784672785449270682527284845249763","seed":1903422557619808550262567587939255293989520784672785449270682527284845249763,"line":277,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 8351.794815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.56362818929174259617209099628199432887635397473273359944166954405559369082746","seed":56362818929174259617209099628199432887635397473273359944166954405559369082746,"line":215,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 2439.758265 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.36371822492296650172705715920975894685324306327803157018631698871644324101908","seed":36371822492296650172705715920975894685324306327803157018631698871644324101908,"line":265,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 10011.969240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.43013703749722695921377805650373614065287390684703305080757260176685746432868","seed":43013703749722695921377805650373614065287390684703305080757260176685746432868,"line":329,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 2689.179664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"2.chip_sw_rv_core_ibex_lockstep_glitch.9655611950856600867465691028308252304925161296804546442738556592617165236444","seed":9655611950856600867465691028308252304925161296804546442738556592617165236444,"line":324,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 2565.242778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.70546135490822131478634013755539377688584118744354759348541755518547163158111","seed":70546135490822131478634013755539377688584118744354759348541755518547163158111,"line":314,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3699.562000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"1.chip_sw_power_idle_load.115474456941605419958997106054255868325578354089835389810958347544971372376121","seed":115474456941605419958997106054255868325578354089835389810958347544971372376121,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3286.531000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"2.chip_sw_power_idle_load.34426796314325551698457296689400172076463143348581662604772914957662618329874","seed":34426796314325551698457296689400172076463143348581662604772914957662618329874,"line":314,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3570.913500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.31446582350013652765600606364861370490761843653988368257147115854801412070232","seed":31446582350013652765600606364861370490761843653988368257147115854801412070232,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 2898.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"1.chip_sw_power_sleep_load.49289663406951319064398134743414937001561432684979439256414561681154485611245","seed":49289663406951319064398134743414937001561432684979439256414561681154485611245,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3324.665000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.57463916178418453488545815324860783929592383653659778968769736003938704729967","seed":57463916178418453488545815324860783929592383653659778968769736003938704729967,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3170.114500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.85745768920208548909637196058675981101983348112911623282545195272152470195440","seed":85745768920208548909637196058675981101983348112911623282545195272152470195440,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11933.051098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.81461559000729183523895114844000413703732263433626352040119999542907687552572","seed":81461559000729183523895114844000413703732263433626352040119999542907687552572,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 10751.659381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.105047412412299707957470973524897060778790333774438002885685148255030009109063","seed":105047412412299707957470973524897060778790333774438002885685148255030009109063,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 13681.046439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.71301428979868498830117022343332529143876257646805622399023724880805211262273","seed":71301428979868498830117022343332529143876257646805622399023724880805211262273,"line":272,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.36749351125971867485839737121165842487662875090436728555825316686171273146206","seed":36749351125971867485839737121165842487662875090436728555825316686171273146206,"line":277,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.85659022646834778571891494854195396064664945229113146076135744346871952203925","seed":85659022646834778571891494854195396064664945229113146076135744346871952203925,"line":272,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.51056802114101443422323619388888943257428553245627463664864642638329937461612","seed":51056802114101443422323619388888943257428553245627463664864642638329937461612,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 16675.467909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.114330177800788326383351701501320748934418567637118930765422510173528253184151","seed":114330177800788326383351701501320748934418567637118930765422510173528253184151,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4473.692031 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4473.692031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.105538890926734803802960432440457322037352236683362244527727643740531319661116","seed":105538890926734803802960432440457322037352236683362244527727643740531319661116,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4694.049968 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4694.049968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.36078977651077921938700846476107297882314815717444047258037112842766257451011","seed":36078977651077921938700846476107297882314815717444047258037112842766257451011,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5717.985350 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5717.985350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.18331093913061173983978225007495199224110638408189566996117672314656381472264","seed":18331093913061173983978225007495199224110638408189566996117672314656381472264,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 26394.634644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.27826523356670025123566761535554857636313773983816864292310289978261070552760","seed":27826523356670025123566761535554857636313773983816864292310289978261070552760,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3093.455143 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.2552648978803630840852118052217749309890707851627140303139194756333057666283","seed":2552648978803630840852118052217749309890707851627140303139194756333057666283,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2826.141195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()":[{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"1.chip_sw_pwrmgr_lowpower_cancel.85614902788605838811447345253257326165065562573048495757371238734520657030644","seed":85614902788605838811447345253257326165065562573048495757371238734520657030644,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 3822.912029 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_transition","qual_name":"3.chip_sw_lc_ctrl_transition.52280117063369432299059883615996085703758695633228391651306507243450313588605","seed":52280117063369432299059883615996085703758695633228391651306507243450313588605,"line":347,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 32210.376062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"11.chip_sw_all_escalation_resets.84916594384024356823601581980319866253921208812754804473509021155488366386259","seed":84916594384024356823601581980319866253921208812754804473509021155488366386259,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3139.615080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"22.chip_sw_all_escalation_resets.90744007416517007093542378093259145468626436444219265617793875818001287615619","seed":90744007416517007093542378093259145468626436444219265617793875818001287615619,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3656.070768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"12.chip_sw_all_escalation_resets.20074866126829979683131757925386040094932323990219170743441416974186046363519","seed":20074866126829979683131757925386040094932323990219170743441416974186046363519,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2846.620812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"29.chip_sw_all_escalation_resets.88619679300520114383553737428738782069191531465962658528422407671826472285951","seed":88619679300520114383553737428738782069191531465962658528422407671826472285951,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3229.043064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"48.chip_sw_all_escalation_resets.16418106244262944663541587958487827614011448223631081682163011790992508193572","seed":16418106244262944663541587958487827614011448223631081682163011790992508193572,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3005.970716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.73137353087086674443872295873429236691499808565716217063027662290778971946326","seed":73137353087086674443872295873429236691499808565716217063027662290778971946326,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3561.922483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1732,"total":2008,"percent":86.25498007968127}