{"block":{"name":"pattgen","variant":null,"commit":"e92b79860e037483a3481cf7b6abda28d3bf4d21","commit_short":"e92b798","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/e92b79860e037483a3481cf7b6abda28d3bf4d21","revision_info":"GitHub Revision: [`e92b798`](https://github.com/lowrisc/opentitan/tree/e92b79860e037483a3481cf7b6abda28d3bf4d21)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-21T15:00:32Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":6.0,"sim_time":841.971855,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":63.81692700000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.327797,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":3.0,"sim_time":744.845961,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":46.378947,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":35.533974,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.327797,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":46.378947,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":63,"total":63,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3602.066647341475,"sim_time":0.0,"passed":35,"total":50,"percent":70.0}},"passed":35,"total":50,"percent":70.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":80.0,"sim_time":2744.262663,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":3.0,"sim_time":15.195482,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10802.096436667256,"sim_time":0.0,"passed":22,"total":50,"percent":44.0}},"passed":22,"total":50,"percent":44.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":42.651449,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":107.787806,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":84.818928,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":84.818928,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":63.81692700000001,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.327797,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":46.378947,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":110.162567,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":63.81692700000001,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.327797,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":46.378947,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":110.162567,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":214,"total":257,"percent":83.26848249027238},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":3.0,"sim_time":461.920054,"passed":25,"total":25,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":61.789984,"passed":5,"total":5,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":3.0,"sim_time":461.920054,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":130.0,"sim_time":5740.910744,"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":239.0,"sim_time":10004.848283,"passed":36,"total":50,"percent":72.0}},"passed":36,"total":50,"percent":72.0}},"passed":36,"total":50,"percent":72.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)":[{"name":"pattgen_inactive_level","qual_name":"0.pattgen_inactive_level.38709953191575668167921434682871094636375243726678694833521652936733182570315","seed":38709953191575668167921434682871094636375243726678694833521652936733182570315,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10025326807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.53434909478102557444311810555962354679986631911651656486161329649800352003427","seed":53434909478102557444311810555962354679986631911651656486161329649800352003427,"line":187,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 12399296276 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 12399296276 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 12399962942 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.92297927407272972050745547790388755447400659264714853576572082884448813340221","seed":92297927407272972050745547790388755447400659264714853576572082884448813340221,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1088801743 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1088801743 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1089201743 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.82871542622567140190341182992619828659159919492659932117643088506401533533704","seed":82871542622567140190341182992619828659159919492659932117643088506401533533704,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5960940720 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5960940720 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 5961940720 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.43133883024855955262152597486388301233552355706371811347268221006367898898952","seed":43133883024855955262152597486388301233552355706371811347268221006367898898952,"line":161,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1200335783 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1200335783 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1200735783 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.82766932017489963441695015369494836858068333822982935701542224506771232963701","seed":82766932017489963441695015369494836858068333822982935701542224506771232963701,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1294556866 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1294556866 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1294723534 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.73785491516119052482096768224737315084747264167508179291399673073282300089225","seed":73785491516119052482096768224737315084747264167508179291399673073282300089225,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3935316943 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3935316943 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3935476943 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.88287753223401485444065724029862198237940786669851110607552112566074550973452","seed":88287753223401485444065724029862198237940786669851110607552112566074550973452,"line":137,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1077429416 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1077429416 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1077533586 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.44116604095078247102375021208590231895080187922221438066714448203445384601904","seed":44116604095078247102375021208590231895080187922221438066714448203445384601904,"line":133,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3426788059 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3426788059 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3426895201 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.22453044585941388112842665001704487779935038154678834543220384056286888401629","seed":22453044585941388112842665001704487779935038154678834543220384056286888401629,"line":124,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 377198065 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 377198065 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 377271747 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.41661223454000904336910869115445307997514116325735187555010689208837893080317","seed":41661223454000904336910869115445307997514116325735187555010689208837893080317,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 219979338 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 219979338 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 220174989 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.13007188728899103429176081976056159673789053022022857421312969477554891232429","seed":13007188728899103429176081976056159673789053022022857421312969477554891232429,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2369408686 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2369408686 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2369475352 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.30000696013112776236692664255506731633495571712250349128957699710175372712526","seed":30000696013112776236692664255506731633495571712250349128957699710175372712526,"line":132,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1067682287 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1067682287 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1067746115 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.112282350968443821789845640227923926497843524040163102183075819585640785159579","seed":112282350968443821789845640227923926497843524040163102183075819585640785159579,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 446121823 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 446121823 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 446496826 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.37207115096862726104360038913070318128567531232316245557185137801064423524608","seed":37207115096862726104360038913070318128567531232316245557185137801064423524608,"line":164,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1527476130 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1527476130 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1527574488 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.88907984334402522309100861556740474719428008239020882022767591458871378136077","seed":88907984334402522309100861556740474719428008239020882022767591458871378136077,"line":154,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 814339701 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 814339701 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 814543781 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.64241015489391416245310298896228257666351897718890672133860541393942596564224","seed":64241015489391416245310298896228257666351897718890672133860541393942596564224,"line":117,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 581406820 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 581406820 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 581436820 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.44802459858640966951101235481847445707564921297544228013726427880546576973934","seed":44802459858640966951101235481847445707564921297544228013726427880546576973934,"line":142,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1144886553 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1144886553 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1144988593 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.4608104149379669762677497770767779074451154096011903956246648873523370631714","seed":4608104149379669762677497770767779074451154096011903956246648873523370631714,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 245879346 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 245879346 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 246025177 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.88149456495471694485887842184186528216946800778859116064862786392067173994766","seed":88149456495471694485887842184186528216946800778859116064862786392067173994766,"line":177,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 693012165 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 693012165 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 693092973 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.57690114052512319985860348444534507228538370408937515544646167034459736533437","seed":57690114052512319985860348444534507228538370408937515544646167034459736533437,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 387048085 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 387048085 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 387333797 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.105474057316039804904357806064895385192446273017175904644914490743286741700186","seed":105474057316039804904357806064895385192446273017175904644914490743286741700186,"line":227,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2591257972 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2591257972 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2591417972 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.30536945658601814790268076445055742485206621767936212629291583090094010885005","seed":30536945658601814790268076445055742485206621767936212629291583090094010885005,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1024128048 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1024128048 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1024231138 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.42959667698488247658469388133120768700533142184643355520548649713810833707462","seed":42959667698488247658469388133120768700533142184643355520548649713810833707462,"line":205,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1100483285 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1100483285 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 1100543285 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.73545273282496259133054540331337333909677322256476791518718014702183605817568","seed":73545273282496259133054540331337333909677322256476791518718014702183605817568,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 422485496 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 422485496 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 422628352 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.12650501197993416368794080089942207621732716924114924763734343091743219394479","seed":12650501197993416368794080089942207621732716924114924763734343091743219394479,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15886643061 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 15886643061 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 15887279424 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.54982215711420222059319076022716387097368571167284178247005115099886697897988","seed":54982215711420222059319076022716387097368571167284178247005115099886697897988,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4552731545 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4552731545 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 4552814879 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.55479237154620756755665551669708500377281549838433941648963716524203055627504","seed":55479237154620756755665551669708500377281549838433941648963716524203055627504,"line":230,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 532580430 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 532580430 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 532691540 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.84434695805778981228305666322859818640817680328680247089622706267377676727614","seed":84434695805778981228305666322859818640817680328680247089622706267377676727614,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7803634390 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7803634390 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 7804062964 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.73358397805527528319532882563465594295219108582032690681081499932887339595666","seed":73358397805527528319532882563465594295219108582032690681081499932887339595666,"line":389,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6029571547 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6029571547 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 9/10\n","UVM_INFO @ 6029731547 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.61925940341553399576839679928338627164831337479967500307521716478672141768791","seed":61925940341553399576839679928338627164831337479967500307521716478672141768791,"line":187,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 585481094 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 585481094 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 585689429 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.67267890569926783559751862334739525612824000306512302309408201061129470178288","seed":67267890569926783559751862334739525612824000306512302309408201061129470178288,"line":170,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 666735379 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 666735379 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 666815379 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.35537857714941269644383555715581903322038235910476734335510023328952312452674","seed":35537857714941269644383555715581903322038235910476734335510023328952312452674,"line":353,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4076951975 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4076951975 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 6/10\n","UVM_INFO @ 4077156055 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.62589873229205271795165345456449770325757922248607817338202023251158095401129","seed":62589873229205271795165345456449770325757922248607817338202023251158095401129,"line":118,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4199661037 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4199661037 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 4199924197 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.90578530113531212836789976722896907816262323643473044432347638498897617068989","seed":90578530113531212836789976722896907816262323643473044432347638498897617068989,"line":175,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 813892990 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 813892990 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 813975462 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.70423704531138220052175835985982312390932322973913903594639112877642276075224","seed":70423704531138220052175835985982312390932322973913903594639112877642276075224,"line":180,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1601304423 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1601304423 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1601488095 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.106175490188489958696230261133952316263034011869537801292321224873565501896592","seed":106175490188489958696230261133952316263034011869537801292321224873565501896592,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 513258947 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 513258947 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 513538947 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.114995590498156188144345638418948738103841625590619387588891527753275256755465","seed":114995590498156188144345638418948738103841625590619387588891527753275256755465,"line":189,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2810821981 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2810821981 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 2811030311 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.49684467310983247528432096787139696154157813030508123171985605416822193814467","seed":49684467310983247528432096787139696154157813030508123171985605416822193814467,"line":114,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 850351404 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 850351404 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 850631404 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.71119614704001219838487141372512676325227768676151924821567444928473918570291","seed":71119614704001219838487141372512676325227768676151924821567444928473918570291,"line":185,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 602629700 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 602629700 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 602711332 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.91494432157605126684020974472512559571835856707661126935106440925479552182234","seed":91494432157605126684020974472512559571835856707661126935106440925479552182234,"line":294,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 49340815648 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 49340815648 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 49342015648 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.58444752101553174016260707771960164097242459182361404583166919408398867838608","seed":58444752101553174016260707771960164097242459182361404583166919408398867838608,"line":116,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1302983168 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1302983168 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1303343168 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.73383882601585073579062784559203309785883048006750837804051303276009974942046","seed":73383882601585073579062784559203309785883048006750837804051303276009974942046,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2777087125 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2777087125 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2777287122 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.84248649266301822927156451158352881159698168700210342205319911288206113901476","seed":84248649266301822927156451158352881159698168700210342205319911288206113901476,"line":402,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3817857295 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3817857295 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 3817888222 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.30865513613237666224303821316189556207813681191316416582493419199804060720557","seed":30865513613237666224303821316189556207813681191316416582493419199804060720557,"line":182,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1278867726 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1278867726 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 1279256618 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.110016242185276174075065885467749487722452225377191698344829046434022286357918","seed":110016242185276174075065885467749487722452225377191698344829046434022286357918,"line":375,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1781711926 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1781711926 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 8/10\n","UVM_INFO @ 1781771926 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"1.pattgen_stress_all.80417995344989680999923763425143960656973450753693179006101027413129097809402","seed":80417995344989680999923763425143960656973450753693179006101027413129097809402,"line":135,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11262\n"]},{"name":"pattgen_stress_all","qual_name":"6.pattgen_stress_all.42216233861303883886357907045673376411775672436887813877688226901950969256040","seed":42216233861303883886357907045673376411775672436887813877688226901950969256040,"line":130,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11318\n"]},{"name":"pattgen_stress_all","qual_name":"8.pattgen_stress_all.30353758694008075729022983428354962647702417046179646547061840350566096669431","seed":30353758694008075729022983428354962647702417046179646547061840350566096669431,"line":135,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11331\n"]},{"name":"pattgen_stress_all","qual_name":"9.pattgen_stress_all.104587661807809863474644190693889070400994039478398950555564370743271460135498","seed":104587661807809863474644190693889070400994039478398950555564370743271460135498,"line":135,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11326\n"]},{"name":"pattgen_stress_all","qual_name":"10.pattgen_stress_all.31734314576148914094212575836013402294555587266682469722634267694806997344142","seed":31734314576148914094212575836013402294555587266682469722634267694806997344142,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11216\n"]},{"name":"pattgen_stress_all","qual_name":"11.pattgen_stress_all.33027390263036226208960710526664449486176211511863280346029794753736263681957","seed":33027390263036226208960710526664449486176211511863280346029794753736263681957,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11389\n"]},{"name":"pattgen_stress_all","qual_name":"14.pattgen_stress_all.82720542158207723785273676783657298150721914584385292042189329234844082937239","seed":82720542158207723785273676783657298150721914584385292042189329234844082937239,"line":142,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11376\n"]},{"name":"pattgen_stress_all","qual_name":"19.pattgen_stress_all.2957155419605837386236355123503466433686084961494926178513519311606410533843","seed":2957155419605837386236355123503466433686084961494926178513519311606410533843,"line":138,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11266\n"]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.78544619490898676801968970441078306799859798699166918218092339476242017441777","seed":78544619490898676801968970441078306799859798699166918218092339476242017441777,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11326\n"]},{"name":"pattgen_stress_all","qual_name":"29.pattgen_stress_all.57582770064792233751837440668219934107593109508442728571665445307646176708737","seed":57582770064792233751837440668219934107593109508442728571665445307646176708737,"line":132,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     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opt/pattgen-sim-xcelium/32.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"32.pattgen_stress_all.74257405840013975669034299611169026842884994331780341729772266152357244244519","seed":74257405840013975669034299611169026842884994331780341729772266152357244244519,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"33.pattgen_perf.43548713780461723549491762712846726072758407213870399554217766473087854643426","seed":43548713780461723549491762712846726072758407213870399554217766473087854643426,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"34.pattgen_perf.25292359926191364648136935643002110287845389017707224324634282296041057189302","seed":25292359926191364648136935643002110287845389017707224324634282296041057189302,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"35.pattgen_perf.82479082878549984153536401271569093695852734989126942764809580858625716834206","seed":82479082878549984153536401271569093695852734989126942764809580858625716834206,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"38.pattgen_stress_all.88378426879984457730710936668527827022084574416940631068321901804075081836387","seed":88378426879984457730710936668527827022084574416940631068321901804075081836387,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"47.pattgen_stress_all.115328873107346344566939647825423662896271688360968184947850109638735901418458","seed":115328873107346344566939647825423662896271688360968184947850109638735901418458,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all/latest/run.log","log_context":[]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"pattgen_inactive_level","qual_name":"2.pattgen_inactive_level.42578094671948578039515664918804397155691419062919372323719889642170073231069","seed":42578094671948578039515664918804397155691419062919372323719889642170073231069,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10017503597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"44.pattgen_inactive_level.115463322628814810666197938649558086030210630578785824079287617773481548378994","seed":115463322628814810666197938649558086030210630578785824079287617773481548378994,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10060371016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"4.pattgen_inactive_level.91928462751303812848805092949057537087150223668138222357165225439292425141156","seed":91928462751303812848805092949057537087150223668138222357165225439292425141156,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10004043601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"27.pattgen_inactive_level.16794373490133451978076420956119304945967309094055554252849432581975050366180","seed":16794373490133451978076420956119304945967309094055554252849432581975050366180,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10030052670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"6.pattgen_perf.108048016536807386703765116481130146820375765348298885901437671482629796482843","seed":108048016536807386703765116481130146820375765348298885901437671482629796482843,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.31638972251733064787471430333882991359830536971332714067806152837858493723227","seed":31638972251733064787471430333882991359830536971332714067806152837858493723227,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"21.pattgen_perf.71593386805185712830970941662700303649197248317199309597936425848094735844275","seed":71593386805185712830970941662700303649197248317199309597936425848094735844275,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"24.pattgen_perf.100990068050233283640693427921159203075946075111878068753223779161008522187435","seed":100990068050233283640693427921159203075946075111878068753223779161008522187435,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/24.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"25.pattgen_perf.55072120262956840374131779564480580044369974905795142070108349970792636301351","seed":55072120262956840374131779564480580044369974905795142070108349970792636301351,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"36.pattgen_perf.84726120297078307697451948095643547291579793880810926453911152947017448216141","seed":84726120297078307697451948095643547291579793880810926453911152947017448216141,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_stress_all","qual_name":"37.pattgen_stress_all.98960948946450068979947610538536661932361542094803558204439420523713145160022","seed":98960948946450068979947610538536661932361542094803558204439420523713145160022,"line":118,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log","log_context":["UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"40.pattgen_perf.88455557486186742668191276674405255754296701516515203448559039945232813759019","seed":88455557486186742668191276674405255754296701516515203448559039945232813759019,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"6.pattgen_inactive_level.33815938431435685776830671959628460413797717039843584793875885734783796852249","seed":33815938431435685776830671959628460413797717039843584793875885734783796852249,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10045756397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"43.pattgen_inactive_level.65161684483964501346080718735495139346374388667876576554036118982747777705132","seed":65161684483964501346080718735495139346374388667876576554036118982747777705132,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10006050989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)":[{"name":"pattgen_inactive_level","qual_name":"10.pattgen_inactive_level.13290664078667692657512588230590667034376419574572098669978013390423856794234","seed":13290664078667692657512588230590667034376419574572098669978013390423856794234,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10016053767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"21.pattgen_inactive_level.437919564986233632074618644609997392087078141095107176758664746625956500540","seed":437919564986233632074618644609997392087078141095107176758664746625956500540,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10040858652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)":[{"name":"pattgen_inactive_level","qual_name":"18.pattgen_inactive_level.3448891107910405234188685823822851089809837743356752330990767576922767871935","seed":3448891107910405234188685823822851089809837743356752330990767576922767871935,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10004848283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)":[{"name":"pattgen_inactive_level","qual_name":"31.pattgen_inactive_level.14784358157821741238223904037387680658202698929004121262709270980980895253362","seed":14784358157821741238223904037387680658202698929004121262709270980980895253362,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10042178700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.60803227926023264821039210001845665030070308702282706147014585220116387566837","seed":60803227926023264821039210001845665030070308702282706147014585220116387566837,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.45577183779215991512804623382879545149583899773711022162819355813024142460547","seed":45577183779215991512804623382879545149583899773711022162819355813024142460547,"line":137,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25)":[{"name":"pattgen_inactive_level","qual_name":"37.pattgen_inactive_level.87588699604795124564975753786839090253591887152158990366646198572485420699777","seed":87588699604795124564975753786839090253591887152158990366646198572485420699777,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10098749270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)":[{"name":"pattgen_inactive_level","qual_name":"41.pattgen_inactive_level.111306901424367297075551754233323434465563802861227025641242885978405984066134","seed":111306901424367297075551754233323434465563802861227025641242885978405984066134,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10072088085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"45.pattgen_inactive_level.49305371270162784984958827749092157502704458386740558730686512524091785647127","seed":49305371270162784984958827749092157502704458386740558730686512524091785647127,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10003509524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":339,"total":443,"percent":76.52370203160271}