{"block":{"name":"chip","variant":null,"commit":"32edacb68e9a736ae5909ca16949f5c4ce181520","commit_short":"32edacb","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/32edacb68e9a736ae5909ca16949f5c4ce181520","revision_info":"GitHub Revision: [`32edacb`](https://github.com/lowrisc/opentitan/tree/32edacb68e9a736ae5909ca16949f5c4ce181520)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-24T04:19:36Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_flash":{"max_time":225.38,"sim_time":2873.4531519999996,"passed":3,"total":3,"percent":100.0},"chip_sw_example_rom":{"max_time":110.44,"sim_time":2139.103996,"passed":3,"total":3,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":235.33,"sim_time":3242.585849,"passed":3,"total":3,"percent":100.0},"chip_sw_example_concurrency":{"max_time":231.61,"sim_time":3041.45707,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":436.79,"sim_time":6506.719274,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":645.77,"sim_time":6323.237969,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":414.99,"sim_time":4995.993673999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":6401.14,"sim_time":37984.83988,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":779.23,"sim_time":9557.541019,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":6401.14,"sim_time":37984.83988,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":645.77,"sim_time":6323.237969,"passed":5,"total":5,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":11.79,"sim_time":224.789123,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":415.21,"sim_time":4473.91612,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":415.21,"sim_time":4473.91612,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":415.21,"sim_time":4473.91612,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":525.49,"sim_time":5033.63132,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":525.49,"sim_time":5033.63132,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":485.43,"sim_time":4630.360658,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":501.88,"sim_time":4535.433321,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":500.44999999999993,"sim_time":4455.73915,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":2619.9,"sim_time":12971.773596,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":2289.61,"sim_time":13485.607725,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":1328.17,"sim_time":13227.531471,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":125,"total":128,"percent":97.65625},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":324.57,"sim_time":5654.047488,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":324.57,"sim_time":5654.047488,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":248.1,"sim_time":3049.9415,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":337.33,"sim_time":6392.668979,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":286.66,"sim_time":4130.097589999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":1189.18,"sim_time":13885.672593000001,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":709.11,"sim_time":9470.777454,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":554.33,"sim_time":6903.002206,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1510.17,"sim_time":17767.199028,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_pattgen_ios":{"tests":{"chip_sw_pattgen_ios":{"max_time":265.55,"sim_time":3725.491682,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pwm_pulses":{"tests":{"chip_sw_sleep_pwm_pulses":{"max_time":1029.73,"sim_time":9270.3433,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":684.37,"sim_time":6459.8273580000005,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":684.37,"sim_time":6459.8273580000005,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":878.86,"sim_time":8234.277105000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":1738.97,"sim_time":13507.709327,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":511.3,"sim_time":4064.8580380000008,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":806.67,"sim_time":6134.225251,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5004.4,"sim_time":19166.932349,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":232.32,"sim_time":2471.461427,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":998.49,"sim_time":7711.045623,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":251.72,"sim_time":3562.63798,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2284.93,"sim_time":12101.103333000001,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":270.24,"sim_time":3160.522781,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.03,"sim_time":5850.867955,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":177.38,"sim_time":2345.385417,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":290.58,"sim_time":3768.172464,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":886.71,"sim_time":9514.008393,"passed":5,"total":5,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":359.31,"sim_time":6030.645896,"passed":3,"total":3,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":248.12999999999997,"sim_time":2994.655685,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":359.31,"sim_time":6030.645896,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_smoketest":{"tests":{"chip_sw_flash_scrambling_smoketest":{"max_time":231.96,"sim_time":3163.532006,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_smoketest":{"max_time":249.47,"sim_time":2996.778222,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":287.07,"sim_time":3377.73155,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":205.79,"sim_time":3454.55546,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":212.49,"sim_time":2773.6602000000003,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":1353.6,"sim_time":8190.39851,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":241.42,"sim_time":3374.8947319999997,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":290.51,"sim_time":3754.362665,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":262.45,"sim_time":3140.767418,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":1959.35,"sim_time":10093.798738,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":329.26,"sim_time":6259.161957,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":404.8,"sim_time":6364.445915,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":230.6,"sim_time":3125.1360090000003,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":224.84,"sim_time":3000.1096669999997,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":226.26,"sim_time":2717.6425520000003,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":218.39,"sim_time":2961.33314,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":227.71,"sim_time":2911.964088,"passed":3,"total":3,"percent":100.0}},"passed":51,"total":51,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":226.44,"sim_time":3204.3327179999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":457.21,"sim_time":5140.981516,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":13282.51,"sim_time":62815.126864,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":3864.5,"sim_time":15016.578201999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":89.62202237080783,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":272.48,"sim_time":3616.411,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":250.83999999999997,"sim_time":3576.87,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":11762.68,"sim_time":55778.262969999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":12392.22,"sim_time":58576.136797,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":491.7300000000001,"sim_time":4778.952392,"passed":2,"total":30,"percent":6.666666666666667}},"passed":2,"total":30,"percent":6.666666666666667},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":491.7300000000001,"sim_time":4778.952392,"passed":2,"total":30,"percent":6.666666666666667}},"passed":2,"total":30,"percent":6.666666666666667},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":6401.14,"sim_time":37984.83988,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":3671.8299999999995,"sim_time":28503.231132,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":436.79,"sim_time":6506.719274,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":645.77,"sim_time":6323.237969,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":6401.14,"sim_time":37984.83988,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":3671.8299999999995,"sim_time":28503.231132,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":436.79,"sim_time":6506.719274,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":645.77,"sim_time":6323.237969,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":79.87,"sim_time":2067.94803,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":8.17,"sim_time":54.634543,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":108.75,"sim_time":10346.730397,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":104.12,"sim_time":7185.839935,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":54.14,"sim_time":601.135141,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":432.84,"sim_time":54820.380848,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":435.0,"sim_time":34407.589043,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":54.5,"sim_time":1466.6784750000002,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":50.71,"sim_time":1334.339542,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":76.94,"sim_time":2412.711239,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":50.71,"sim_time":1334.339542,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":131.22,"sim_time":3101.470577,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":1151.26,"sim_time":88770.15002599999,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":74.07,"sim_time":2267.8237940000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":573.0,"sim_time":19517.883741,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":454.44,"sim_time":15408.624770999999,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":1098.58,"sim_time":30464.332042,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":590.6,"sim_time":18516.2821,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":3864.5,"sim_time":15016.578201999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":3671.4,"sim_time":30201.376996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":3787.8599999999997,"sim_time":16500.636413,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":166.33078391477466,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":11.524240231141448,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":11.584155537188053,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":11.533455812372267,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":10.507971835322678,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":185.0940035060048,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":9.258584374561906,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":12.030109728686512,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":11.901330141350627,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":11.750185898505151,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":93.48636096622795,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":18.18092723377049,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":17.524315748363733,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":18.39856909867376,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":15.83617233671248,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":119.29062769655138,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":17.646683344617486,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":22.229577152058482,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":24.88141744211316,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":20.74973951932043,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":23.45274763647467,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":21.168255737051368,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":19.39170351997018,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":20.018068321980536,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":20.330849296413362,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":31.475971814244986,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":43.76910954527557,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":20.282778637483716,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":25.719739546068013,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":19.032609337940812,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":107.72232543025166,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":11.566250313073397,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":11.577158032916486,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":11.677744563668966,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":13.212586672976613,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":8060.870000000001,"sim_time":29593.179275,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":7787.949999999999,"sim_time":29821.373420000004,"passed":1,"total":3,"percent":33.333333333333336},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":7601.540000000001,"sim_time":28863.784866,"passed":3,"total":3,"percent":100.0}},"passed":7,"total":9,"percent":77.77777777777777},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":4092.4999999999995,"sim_time":17235.694583,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1616277843714,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1616277843714,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":283.23,"sim_time":3302.589494,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":232.32,"sim_time":2471.461427,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":226.17,"sim_time":2592.874048,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":240.26,"sim_time":3381.990265,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":2116.86,"sim_time":12370.99788,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":269.4,"sim_time":3791.276324,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":527.56,"sim_time":6348.478127,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":754.28,"sim_time":5132.674139000001,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":354.07,"sim_time":3849.369947,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":506.0,"sim_time":4639.776298000001,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":345.1,"sim_time":3851.6088339999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1477.28,"sim_time":11274.032838,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":452.25,"sim_time":5326.83875,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":267.97,"sim_time":3213.6712799999996,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":14400.163921914062,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1449.24,"sim_time":7703.627495,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1178.57,"sim_time":7218.044634,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":1052.48,"sim_time":8018.6793959999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":13755.64,"sim_time":255901.782552,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":391.91,"sim_time":4683.995676,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":329.26,"sim_time":6259.161957,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":391.91,"sim_time":4683.995676,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":693.42,"sim_time":7517.776457000001,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":693.42,"sim_time":7517.776457000001,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":481.99,"sim_time":7163.724837000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":546.36,"sim_time":6201.8097609999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":787.88,"sim_time":6047.154338,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":240.26,"sim_time":3381.990265,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":222.82,"sim_time":3604.389622,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":210.03,"sim_time":3081.512236,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":431.23,"sim_time":4284.571632,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":453.46,"sim_time":5228.76208,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":390.4,"sim_time":4074.344233,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":468.82,"sim_time":5915.859423999999,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":1167.82,"sim_time":10513.94482,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":545.81,"sim_time":4338.90038,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":506.45000000000005,"sim_time":4353.851326,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":488.47,"sim_time":4059.926054,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":523.93,"sim_time":4539.411623999999,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":520.13,"sim_time":4103.001765,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":556.21,"sim_time":4968.582063,"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":878.86,"sim_time":8234.277105000001,"passed":3,"total":3,"percent":100.0}},"passed":21,"total":21,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":706.64,"sim_time":11540.531808,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":488.47,"sim_time":4059.926054,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":523.93,"sim_time":4539.411623999999,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":511.3,"sim_time":4064.8580380000008,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":806.67,"sim_time":6134.225251,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5004.4,"sim_time":19166.932349,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":232.32,"sim_time":2471.461427,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":998.49,"sim_time":7711.045623,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":251.72,"sim_time":3562.63798,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2284.93,"sim_time":12101.103333000001,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":270.24,"sim_time":3160.522781,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.03,"sim_time":5850.867955,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":177.38,"sim_time":2345.385417,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":210.91,"sim_time":3277.222663,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":481.41,"sim_time":5135.5027549999995,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":889.52,"sim_time":8086.063585,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":4910.01,"sim_time":25221.002838,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":222.95,"sim_time":3328.2496929999998,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":219.44,"sim_time":3531.8532889999997,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":1410.36,"sim_time":11954.570381,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":244.21000000000004,"sim_time":3603.430182,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":464.74,"sim_time":5257.878743,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1836.38,"sim_time":27183.418336,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":28800.158528060656,"sim_time":0.0,"passed":2,"total":3,"percent":66.66666666666667}},"passed":32,"total":33,"percent":96.96969696969697},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":878.86,"sim_time":8234.277105000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":518.47,"sim_time":4314.775074,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":356.26,"sim_time":3893.6387480000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1449.24,"sim_time":7703.627495,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3055.72,"sim_time":24516.683149999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":346.6,"sim_time":4583.088565,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":664.62,"sim_time":8440.186708000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":241.29999999999998,"sim_time":2970.7918059999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":5364.35,"sim_time":22194.617140000002,"passed":10,"total":10,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":265.5,"sim_time":3603.737133,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":957.04,"sim_time":7614.484692,"passed":3,"total":3,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":265.5,"sim_time":3603.737133,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3055.72,"sim_time":24516.683149999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":189.73,"sim_time":3164.800526,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init":{"tests":{"chip_sw_flash_init":{"max_time":1774.73,"sim_time":23440.41531,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_host_access":{"tests":{"chip_sw_flash_ctrl_access":{"max_time":781.56,"sim_time":5934.509845,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":806.67,"sim_time":6134.225251,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_ctrl_ops":{"tests":{"chip_sw_flash_ctrl_ops":{"max_time":479.28,"sim_time":3999.9836299999997,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":511.3,"sim_time":4064.8580380000008,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_rma_unlocked":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4948.39,"sim_time":44351.373207000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_scramble":{"tests":{"chip_sw_flash_init":{"max_time":1774.73,"sim_time":23440.41531,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_idle_low_power":{"tests":{"chip_sw_flash_ctrl_idle_low_power":{"max_time":326.07,"sim_time":4063.608888,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_keymgr_seeds":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_creator_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_creator_seed_wipe_on_rma":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4948.39,"sim_time":44351.373207000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_owner_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_wr_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_seed_hw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_escalate_en":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_flash_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":406.71,"sim_time":12431.549536,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"tests":{"chip_sw_flash_ctrl_clock_freqs":{"max_time":755.73,"sim_time":5348.166696,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_escalation_reset":{"tests":{"chip_sw_flash_crash_alert":{"max_time":617.6,"sim_time":5150.718955,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"tests":{"chip_sw_flash_crash_alert":{"max_time":617.6,"sim_time":5150.718955,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":257.11,"sim_time":3819.11124,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":251.72,"sim_time":3562.63798,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":222.82,"sim_time":3604.389622,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":1367.94,"sim_time":8069.294224,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":980.78,"sim_time":5886.176376,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":509.85,"sim_time":4647.1768839999995,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":580.15,"sim_time":5227.193327999999,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":547.69,"sim_time":5555.115056,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":380.0,"sim_time":3383.794952,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2284.93,"sim_time":12101.103333000001,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"tests":{"chip_sw_keymgr_sideload_kmac":{"max_time":1863.8,"sim_time":11250.163702,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":2116.86,"sim_time":12370.99788,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"tests":{"chip_sw_keymgr_sideload_otbn":{"max_time":3757.04,"sim_time":15012.031559000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":213.55,"sim_time":2781.702572,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":242.93,"sim_time":2794.69527,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":270.24,"sim_time":3160.522781,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":247.88,"sim_time":3090.7694539999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":914.81,"sim_time":6364.602184,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":210.03,"sim_time":3081.512236,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":527.56,"sim_time":6348.478127,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":1189.18,"sim_time":13885.672593000001,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":554.33,"sim_time":6903.002206,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1510.17,"sim_time":17767.199028,"passed":5,"total":5,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":212.83,"sim_time":2627.5150639999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_key_derivation_prod":{"max_time":2220.07,"sim_time":12836.269244000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":200.45,"sim_time":3070.56038,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_rma_unlocked":{"max_time":4948.39,"sim_time":44351.373207000004,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":297.15,"sim_time":3703.7772400000003,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":745.65,"sim_time":8070.606957999999,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":624.33,"sim_time":6596.706964,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":684.45,"sim_time":7348.580266,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":444.24,"sim_time":9888.326640000001,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":617.47,"sim_time":9452.894969,"passed":3,"total":3,"percent":100.0},"chip_prim_tl_access":{"max_time":406.71,"sim_time":12431.549536,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":706.64,"sim_time":11540.531808,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":545.81,"sim_time":4338.90038,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":506.45000000000005,"sim_time":4353.851326,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":488.47,"sim_time":4059.926054,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":523.93,"sim_time":4539.411623999999,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":520.13,"sim_time":4103.001765,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":556.21,"sim_time":4968.582063,"passed":3,"total":3,"percent":100.0},"chip_tap_straps_dev":{"max_time":1189.18,"sim_time":13885.672593000001,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":554.33,"sim_time":6903.002206,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1510.17,"sim_time":17767.199028,"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":208.99,"sim_time":5483.691609,"passed":0,"total":3,"percent":0.0}},"passed":75,"total":84,"percent":89.28571428571429},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":264.4,"sim_time":3919.527475,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":97.47,"sim_time":3638.969466,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":119.23,"sim_time":2953.263324,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":2454.17,"sim_time":26717.951511,"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":6,"percent":83.33333333333333},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":2102.92,"sim_time":25485.677030000003,"passed":2,"total":3,"percent":66.66666666666667},"chip_rv_dm_lc_disabled":{"max_time":208.99,"sim_time":5483.691609,"passed":0,"total":3,"percent":0.0}},"passed":2,"total":6,"percent":33.333333333333336},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":846.47,"sim_time":8780.453884,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":962.8799999999999,"sim_time":11784.032471999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":891.73,"sim_time":10965.183716,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":574.63,"sim_time":7643.110568,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":2102.92,"sim_time":25485.677030000003,"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":15,"percent":33.333333333333336},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":110.2,"sim_time":2357.1655950000004,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":85.3,"sim_time":2720.7758369999997,"passed":3,"total":3,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":114.28230930771679,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":6,"total":9,"percent":66.66666666666667},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":4912.48,"sim_time":17868.078576,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5004.4,"sim_time":19166.932349,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":787.88,"sim_time":6047.154338,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":787.88,"sim_time":6047.154338,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":787.88,"sim_time":6047.154338,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":402.13,"sim_time":3455.6826140000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_flash_init":{"max_time":1774.73,"sim_time":23440.41531,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":402.13,"sim_time":3455.6826140000003,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":601.1,"sim_time":4858.777892,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":248.47000000000003,"sim_time":3046.1784470000002,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_flash_init":{"max_time":1774.73,"sim_time":23440.41531,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":402.13,"sim_time":3455.6826140000003,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2186.19,"sim_time":13085.639019999999,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":601.1,"sim_time":4858.777892,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":248.47000000000003,"sim_time":3046.1784470000002,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":522.81,"sim_time":5270.550641,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":212.83,"sim_time":2627.5150639999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":297.15,"sim_time":3703.7772400000003,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":745.65,"sim_time":8070.606957999999,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":624.33,"sim_time":6596.706964,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":684.45,"sim_time":7348.580266,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":858.56,"sim_time":10375.364378,"passed":15,"total":15,"percent":100.0},"chip_prim_tl_access":{"max_time":406.71,"sim_time":12431.549536,"passed":3,"total":3,"percent":100.0}},"passed":27,"total":30,"percent":90.0},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":406.71,"sim_time":12431.549536,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":1127.79,"sim_time":7999.0053880000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":270.8,"sim_time":6584.628992,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1495.5,"sim_time":29058.989708,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":375.35,"sim_time":7676.3482300000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":453.59,"sim_time":7687.642,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":668.52,"sim_time":7464.992566,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1310.64,"sim_time":22494.178708,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":1065.65,"sim_time":13101.780061000001,"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":693.42,"sim_time":7517.776457000001,"passed":1,"total":3,"percent":33.333333333333336}},"passed":2,"total":6,"percent":33.333333333333336},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":1233.39,"sim_time":10089.623003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":473.8,"sim_time":5652.671034,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_aon_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":270.8,"sim_time":6584.628992,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":461.7,"sim_time":4627.97682,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":1507.65,"sim_time":16447.492059,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":349.51,"sim_time":7543.613346,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":223.17,"sim_time":2955.756375,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":999.27,"sim_time":14011.4975,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1119.59,"sim_time":9236.238118000001,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1572.13,"sim_time":12112.375959,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":2383.75,"sim_time":35566.360844999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":270.42,"sim_time":3698.431078,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":444.24,"sim_time":9888.326640000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":444.24,"sim_time":9888.326640000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1572.13,"sim_time":12112.375959,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":999.27,"sim_time":14011.4975,"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"max_time":473.8,"sim_time":5652.671034,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":329.26,"sim_time":6259.161957,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":12,"percent":75.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":408.85,"sim_time":4833.110067,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":557.37,"sim_time":6828.965694,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":422.73,"sim_time":4795.632216,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1477.28,"sim_time":11274.032838,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":248.7,"sim_time":3053.615022,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1178.57,"sim_time":7218.044634,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":638.14,"sim_time":4549.641472,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":652.49,"sim_time":4275.917934,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":264.34,"sim_time":3518.897469,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":248.47000000000003,"sim_time":3046.1784470000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":557.37,"sim_time":6828.965694,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":557.37,"sim_time":6828.965694,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":1721.23,"sim_time":18747.62076,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":1307.48,"sim_time":13448.1718,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":408.85,"sim_time":4833.110067,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":293.87,"sim_time":3339.2412560000002,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":490.05,"sim_time":6661.03212,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":554.33,"sim_time":6903.002206,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":208.99,"sim_time":5483.691609,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":754.28,"sim_time":5132.674139000001,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":354.07,"sim_time":3849.369947,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":506.0,"sim_time":4639.776298000001,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":226.38,"sim_time":2844.331594,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":253.70000000000002,"sim_time":3307.457824,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":3864.5,"sim_time":15016.578201999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":518.98,"sim_time":6040.507488,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":313.63,"sim_time":3034.26022,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":310.28,"sim_time":4014.9649529999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":277.03,"sim_time":3579.95088,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":601.1,"sim_time":4858.777892,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.03,"sim_time":5850.867955,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":632.72,"sim_time":8134.086974999999,"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":560.36,"sim_time":8008.361900000001,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":617.47,"sim_time":9452.894969,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0},"chip_sw_data_integrity_escalation":{"max_time":684.37,"sim_time":6459.8273580000005,"passed":6,"total":6,"percent":100.0}},"passed":93,"total":106,"percent":87.73584905660377},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1119.59,"sim_time":9236.238118000001,"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1681.21,"sim_time":25298.743728999998,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":234.79,"sim_time":3744.650937,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":320.4,"sim_time":3798.892113,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":417.87,"sim_time":5418.083979,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1681.21,"sim_time":25298.743728999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1681.21,"sim_time":25298.743728999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3187.62,"sim_time":20035.338219999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3187.62,"sim_time":20035.338219999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":468.54,"sim_time":6727.813912,"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.1616277843714,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":228.84,"sim_time":3071.510012,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":175.18,"sim_time":2835.804348,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":426.88,"sim_time":4517.708036,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":387.15,"sim_time":4474.774091,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":1241.55,"sim_time":8516.026722999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":6924.41,"sim_time":31693.002055,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":2236.42,"sim_time":12622.301208,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":245.08999999999997,"sim_time":3073.713624,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1544,"total":1799,"percent":85.8254585881045},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":218.44,"sim_time":3409.006879,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":127.7,"sim_time":2920.111132,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":16634.22,"sim_time":71634.156296,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":1500.96,"sim_time":6544.6221749999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":303.09,"sim_time":4337.767713,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":241.8,"sim_time":3326.7839900000004,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":244.62,"sim_time":4172.36037,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":19.030338783748448,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":18.745270557701588,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":18.715198487974703,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":86.71160158608109,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":390.66,"sim_time":3251.6022059999996,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":485.26000000000005,"sim_time":3235.77065,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":652.77,"sim_time":3612.4999900000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":2069.15,"sim_time":11108.180888,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":328.52,"sim_time":2483.634642,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_memory_protection":{"tests":{"chip_sw_flash_ctrl_mem_protection":{"max_time":816.78,"sim_time":5790.185724000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":235.69,"sim_time":3413.9399670000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":225.35,"sim_time":3132.6295800000003,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":433.39,"sim_time":6889.714296,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":425.78,"sim_time":5012.606288,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1572.13,"sim_time":12112.375959,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":303.09,"sim_time":4337.767713,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":241.8,"sim_time":3326.7839900000004,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":244.62,"sim_time":4172.36037,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":503.34999999999997,"sim_time":6386.920567,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":644.47,"sim_time":6039.778765999999,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.167209818959,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.167209818959,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":232.61,"sim_time":3730.2044530000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":525.49,"sim_time":5033.63132,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":3911.5199999999995,"sim_time":19189.801635000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":130,"total":159,"percent":81.76100628930817},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sival_flash_info_access":{"max_time":280.59,"sim_time":3114.539103,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":580.93,"sim_time":5857.531120000001,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":8.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":268.27,"sim_time":3328.232803,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":248.74,"sim_time":3482.917287,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":344.32,"sim_time":3800.200816,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":11.05874053016305,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_ctrl_write_clear":{"max_time":277.14,"sim_time":3125.37397,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_flash_erase":{"max_time":800.59,"sim_time":10010.220001,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":9798.76,"sim_time":44876.168712,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_disjoint":{"max_time":10800.167065409943,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":21,"total":31,"percent":67.74193548387096}},"passed":21,"total":31,"percent":67.74193548387096}},"coverage":{"code":{"block":null,"line_statement":94.82,"branch":94.95,"condition_expression":93.35,"toggle":91.72,"fsm":57.14},"assertion":97.87,"functional":99.37},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Offending '(!$isunknown(pin_wkup_req_o))'":[{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.77905894180052107980065354591961531129823981196642221831296425564575697055725","seed":77905894180052107980065354591961531129823981196642221831296425564575697055725,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_ERROR @ 2604.277500 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A\n","UVM_INFO @ 2604.277500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.6916007874932327146643427545480062128418964878536152626628786810269933333665","seed":6916007874932327146643427545480062128418964878536152626628786810269933333665,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3034.260220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.65638020374432354671937601560712231003002251098244273514104728895918600795805","seed":65638020374432354671937601560712231003002251098244273514104728895918600795805,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3217.405707 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.76317413286314679843176600448422359030339337935961932861955448550031512785330","seed":76317413286314679843176600448422359030339337935961932861955448550031512785330,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3365.207119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.47937970017889027155574642749406314608857919479231722845775621839062271461771","seed":47937970017889027155574642749406314608857919479231722845775621839062271461771,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3289.473636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"1.chip_sw_flash_ctrl_lc_rw_en.114952292799293439135857294989282574622353451920357340478703125075762844328687","seed":114952292799293439135857294989282574622353451920357340478703125075762844328687,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3070.560380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"2.chip_sw_flash_ctrl_lc_rw_en.2957877770329825346068002501608643965714089593866708513297712001637939345111","seed":2957877770329825346068002501608643965714089593866708513297712001637939345111,"line":309,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 2594.815864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.115302441391960096512619601086840959245704540484466619185590160937369335138589","seed":115302441391960096512619601086840959245704540484466619185590160937369335138589,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6926.368734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.40600235020375477077142677558156859422842354793659653212124667246801458120982","seed":40600235020375477077142677558156859422842354793659653212124667246801458120982,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7655.575159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.90348735539182694532427502299596910398867307826339157129846888706461167022178","seed":90348735539182694532427502299596910398867307826339157129846888706461167022178,"line":342,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7348.580266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.57801914912907588821660715204374698559370497873614310358681586548703440078220","seed":57801914912907588821660715204374698559370497873614310358681586548703440078220,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 3132.629580 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3132.629580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.109524311772542416318635352153158181235653447232635193188877167564386181028686","seed":109524311772542416318635352153158181235653447232635193188877167564386181028686,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3217.571272 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3217.571272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.81380369395178475375948264856226846888322568639076029883120594884606028676072","seed":81380369395178475375948264856226846888322568639076029883120594884606028676072,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 2638.857910 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2638.857910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"3.chip_sw_all_escalation_resets.30409761577182022057498183898569861197932864449853494476124108413530274350626","seed":30409761577182022057498183898569861197932864449853494476124108413530274350626,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2716.278048 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2716.278048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"4.chip_sw_all_escalation_resets.29239039329764006410680773285539356740546354584612205675228748358696300796443","seed":29239039329764006410680773285539356740546354584612205675228748358696300796443,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2848.250952 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2848.250952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"38.chip_sw_all_escalation_resets.472379935962215538846851136027618191786852525229511889408800829818541951642","seed":472379935962215538846851136027618191786852525229511889408800829818541951642,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2914.095324 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2914.095324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"42.chip_sw_all_escalation_resets.18086942583633581137117390748275111437362609423570368775725751141419112923846","seed":18086942583633581137117390748275111437362609423570368775725751141419112923846,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2741.804412 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2741.804412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"77.chip_sw_all_escalation_resets.79716135166940431384726851623826231801788311675753667763535921173367305050172","seed":79716135166940431384726851623826231801788311675753667763535921173367305050172,"line":322,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3151.978988 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3151.978988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"89.chip_sw_all_escalation_resets.33779418905044824446987111042597892726743193003286122419038676172907549967261","seed":33779418905044824446987111042597892726743193003286122419038676172907549967261,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3511.567040 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3511.567040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.58050190564825787865529011422998549849799267155352488416107799275330300137153","seed":58050190564825787865529011422998549849799267155352488416107799275330300137153,"line":282,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rand_to_scrap.77547955004812060251308048762204990405822645646281224682411292564031802664377","seed":77547955004812060251308048762204990405822645646281224682411292564031802664377,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_INFO @ 26717.951511 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.40601448571644389329636050509170548515541303439599783856640500691242389476915","seed":40601448571644389329636050509170548515541303439599783856640500691242389476915,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9245.355688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.71525620337085010129403143678246970040664879007430486853267785700515178209417","seed":71525620337085010129403143678246970040664879007430486853267785700515178209417,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 11784.032472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.62810762340223437846250456336867224854990046450746263226456947345024749141676","seed":62810762340223437846250456336867224854990046450746263226456947345024749141676,"line":341,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7643.110568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.33208219808590088796855863738031703004092166090418512667687382933091949468789","seed":33208219808590088796855863738031703004092166090418512667687382933091949468789,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 8992.959775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.44534628897111181842387951908437495508535474844743688821861591976652301232586","seed":44534628897111181842387951908437495508535474844743688821861591976652301232586,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 9413.029925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.82331121545661822172670696737032436620516959515960139662466857449128250121577","seed":82331121545661822172670696737032436620516959515960139662466857449128250121577,"line":341,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 6176.894662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.16236216931288021046785260223961293372235147373375102584573360547344080437931","seed":16236216931288021046785260223961293372235147373375102584573360547344080437931,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 8780.453884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.63462951722135301687370851944329480391679366950224639361420538475096057377088","seed":63462951722135301687370851944329480391679366950224639361420538475096057377088,"line":369,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 10052.219036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.74269146047232730479479530545705433359547642330116902535994412429403131986984","seed":74269146047232730479479530545705433359547642330116902535994412429403131986984,"line":341,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7129.198655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.89300979520902193639708874443057160124677303674035815967968219042612740500153","seed":89300979520902193639708874443057160124677303674035815967968219042612740500153,"line":304,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["UVM_INFO @ 26178.431097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.91698402344730899439504473454799827413285399915705737275470619312253520033680","seed":91698402344730899439504473454799827413285399915705737275470619312253520033680,"line":320,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 6504.870704 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 6504.870704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.93831993146064578749503647571368132012380792043643016596090774136119488010489","seed":93831993146064578749503647571368132012380792043643016596090774136119488010489,"line":230,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4256.705000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 4256.705000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.13112145390721126853906812777963234443265446044630001789032631751022356239843","seed":13112145390721126853906812777963234443265446044630001789032631751022356239843,"line":303,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2921.155853 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2921.155853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.87138892532378681786339818801896403093270432268999516356568936463031006362650","seed":87138892532378681786339818801896403093270432268999516356568936463031006362650,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 6584.628992 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 6584.628992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.712264055272610647221783714961738794066894169715207953728385563444271958504","seed":712264055272610647221783714961738794066894169715207953728385563444271958504,"line":344,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 13281.063500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 13281.063500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.28956520360870952956334149262873705161905045631083794799496983120501004866853","seed":28956520360870952956334149262873705161905045631083794799496983120501004866853,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10488.822000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10488.822000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.6292054823104778807141198657969605074104341884906093794999517980331790821548","seed":6292054823104778807141198657969605074104341884906093794999517980331790821548,"line":325,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7008.172500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7008.172500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.28936685950130375321150042324883634442281973191363322346512761935581957610516","seed":28936685950130375321150042324883634442281973191363322346512761935581957610516,"line":344,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 14011.497500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 14011.497500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.7823771303244964878499104779137275684411349419698120679837235573107696817347","seed":7823771303244964878499104779137275684411349419698120679837235573107696817347,"line":325,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7341.436000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7341.436000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.66721919137119230111080222898044520226807297514291071953493508571967129364510","seed":66721919137119230111080222898044520226807297514291071953493508571967129364510,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8354.610000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8354.610000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.63317491811671514481907530629518551986575582422169995739598092024570403617352","seed":63317491811671514481907530629518551986575582422169995739598092024570403617352,"line":315,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5277.889000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5277.889000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.24211793356862286935217201752755967432052776513672942734945564442326445726391","seed":24211793356862286935217201752755967432052776513672942734945564442326445726391,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 9100.453000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9100.453000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_por_reset.41846683027483465270555293658406196665771783639484986293552899042470583712958","seed":41846683027483465270555293658406196665771783639484986293552899042470583712958,"line":325,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7687.642000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7687.642000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.19740402324473576960806933388930318316356354387105343867168611954148262265903","seed":19740402324473576960806933388930318316356354387105343867168611954148262265903,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7417.426000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7417.426000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.102651093443452214042546182714187827406417616840800010480037142774036808269122","seed":102651093443452214042546182714187827406417616840800010480037142774036808269122,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3294.700968 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3294.700968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.49826875360388053797777255713496462427022375808941134210696976339637835398983","seed":49826875360388053797777255713496462427022375808941134210696976339637835398983,"line":329,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 6766.480800 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 6766.480800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.105333830056478282468867938522847870160248847779224795257802209788440457306248","seed":105333830056478282468867938522847870160248847779224795257802209788440457306248,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2607.783053 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2607.783053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.40337926130152032295654928035604697799179520978619251649926077768617574330219","seed":40337926130152032295654928035604697799179520978619251649926077768617574330219,"line":380,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 16447.492059 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 16447.492059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.19348693240427832458474643885717647536862851399356675623050945861038052765216","seed":19348693240427832458474643885717647536862851399356675623050945861038052765216,"line":313,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2955.756375 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2955.756375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.37852522304280234362273701878143117738547706645029910804270767056067299710148","seed":37852522304280234362273701878143117738547706645029910804270767056067299710148,"line":367,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 18158.416982 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 18158.416982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.17160797756063957918248610784656000965784366389624010556036072841926443466923","seed":17160797756063957918248610784656000965784366389624010556036072841926443466923,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.77724915855322115771321264145492783852726873664733322534076621348352867841346","seed":77724915855322115771321264145492783852726873664733322534076621348352867841346,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.16004276182841476914993640049725865940096270338398335897958598705087136923753","seed":16004276182841476914993640049725865940096270338398335897958598705087136923753,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.100989207431197913581738992472801413430644757653950754676632396304002812428892","seed":100989207431197913581738992472801413430644757653950754676632396304002812428892,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.9935743984905447680639615493612450257628672950466434447302885370091049331039","seed":9935743984905447680639615493612450257628672950466434447302885370091049331039,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.100616923996969888541075408953484246325700291348547715960795084686080132126527","seed":100616923996969888541075408953484246325700291348547715960795084686080132126527,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.58536041757908791102812881278988974451903677017701547295389044039492781343675","seed":58536041757908791102812881278988974451903677017701547295389044039492781343675,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.6103858436761258473585178163415276094111400222196918913838077138489432655904","seed":6103858436761258473585178163415276094111400222196918913838077138489432655904,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.39041899821511727928945984034076647569496588719203433837899377115231461317200","seed":39041899821511727928945984034076647569496588719203433837899377115231461317200,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.101387954051913124467668142836767623866827720939265877405733296337172362800523","seed":101387954051913124467668142836767623866827720939265877405733296337172362800523,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.38982610769440155510306008953668934211964154811592115516399905528556043970888","seed":38982610769440155510306008953668934211964154811592115516399905528556043970888,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.106202389267359548444514082050246658735053755746432215792218562400294001493355","seed":106202389267359548444514082050246658735053755746432215792218562400294001493355,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.115667826039441171834363416737640243835701712011729132425836894187736978719676","seed":115667826039441171834363416737640243835701712011729132425836894187736978719676,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.4776597864413770603767705032232215432255126842075576045405819305643755339255","seed":4776597864413770603767705032232215432255126842075576045405819305643755339255,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3021.198520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.32504210702411879299605239141651058883734871732471597475792132126852140959465","seed":32504210702411879299605239141651058883734871732471597475792132126852140959465,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2693.669704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.60400947315658836470694371999431193518683962286783770162685129756661303606022","seed":60400947315658836470694371999431193518683962286783770162685129756661303606022,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2855.764101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.114538712035052849020818451471953813746236801136046267073233384595607510268322","seed":114538712035052849020818451471953813746236801136046267073233384595607510268322,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2958.608940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.39735591031318743960812566306614086122501324527152918625576269303146060347700","seed":39735591031318743960812566306614086122501324527152918625576269303146060347700,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2959.851439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.55261283510167462914568136347941992896546789802942452456870834469923781466396","seed":55261283510167462914568136347941992896546789802942452456870834469923781466396,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3094.379337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.27017009401446433111147639259199814545278701325877816736102105897936939154078","seed":27017009401446433111147639259199814545278701325877816736102105897936939154078,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2640.772648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.39388390743759060341039618793129857904117349301036731476101623002359775177854","seed":39388390743759060341039618793129857904117349301036731476101623002359775177854,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2872.058725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.52007861603007076031531515159568065384502663976740527209908888113829690872232","seed":52007861603007076031531515159568065384502663976740527209908888113829690872232,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3374.959936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.90364484704554538538927865978177583280966196471228261901201102111624928987041","seed":90364484704554538538927865978177583280966196471228261901201102111624928987041,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3077.941816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.31807996404089881209219861155482212880569642669388884869290349783925065420124","seed":31807996404089881209219861155482212880569642669388884869290349783925065420124,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3279.547758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.61927341250551970395779262259882821084073489823416459715237428089306954740200","seed":61927341250551970395779262259882821084073489823416459715237428089306954740200,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3405.977647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.69964227592519558857103024688311363319138957059368570910270872867836543949818","seed":69964227592519558857103024688311363319138957059368570910270872867836543949818,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3317.588424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.53120595232716671492787777881329569136158015034001742673232708165041977634858","seed":53120595232716671492787777881329569136158015034001742673232708165041977634858,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2601.692108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.30887947820123812605705964061695772735039075478857684163271976967497518001747","seed":30887947820123812605705964061695772735039075478857684163271976967497518001747,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3255.552644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.111031464153410670369338862100818731021090590960573387524329356943967759769031","seed":111031464153410670369338862100818731021090590960573387524329356943967759769031,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2631.157778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.81144610270931100368650806778495010510634732153182594086235733641328935915137","seed":81144610270931100368650806778495010510634732153182594086235733641328935915137,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2609.823772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.12619578461951736636511492110537326455293125065661297436675680159738337517411","seed":12619578461951736636511492110537326455293125065661297436675680159738337517411,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2930.011965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.61094674572317832251248120085233094091610151387656200727217573421274001158038","seed":61094674572317832251248120085233094091610151387656200727217573421274001158038,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2786.562646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.29124741121758266047793486863259462798686961897246155103339581445959047919116","seed":29124741121758266047793486863259462798686961897246155103339581445959047919116,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3316.648212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.99029786667851572893401642762049063893565126848004371815847697831717161551746","seed":99029786667851572893401642762049063893565126848004371815847697831717161551746,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3526.285000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.60687934755649423499059862552628291020645028576817529360674929553290836809898","seed":60687934755649423499059862552628291020645028576817529360674929553290836809898,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3022.390477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.28292183501471175937502237959543192805426109148466807033207378194912025336073","seed":28292183501471175937502237959543192805426109148466807033207378194912025336073,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2811.459816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.96964832181694443226369638722225709077601083880048244664032062891970451355159","seed":96964832181694443226369638722225709077601083880048244664032062891970451355159,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3097.469932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.91592196171360046863647174003972645673107726787853375844930438333943902102122","seed":91592196171360046863647174003972645673107726787853375844930438333943902102122,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2365.148020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.64198242733684929306754007813719503988820018693641457897072388076919527478796","seed":64198242733684929306754007813719503988820018693641457897072388076919527478796,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3095.690562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.21242093172203125229732260932004637863370980862225238900215701831972805973141","seed":21242093172203125229732260932004637863370980862225238900215701831972805973141,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3528.079020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.115389423500048088241691246776310831589392979689960871408508307985647347227070","seed":115389423500048088241691246776310831589392979689960871408508307985647347227070,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2561.314691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.58842733613517480937892056259883267461354451898782451357389551850887164769001","seed":58842733613517480937892056259883267461354451898782451357389551850887164769001,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2919.313670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.7151470351613318039158800687058166806352699774718118050567377854118763272668","seed":7151470351613318039158800687058166806352699774718118050567377854118763272668,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3655.960376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.91155476926117290786291980866157966160824662005013043821037156246982768990663","seed":91155476926117290786291980866157966160824662005013043821037156246982768990663,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3287.512532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.86243323214315286272457134168287416878022436352376083370958443538188364245809","seed":86243323214315286272457134168287416878022436352376083370958443538188364245809,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2739.820275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.110954516557282319013129888282333499665642220178659408192689320746099638078367","seed":110954516557282319013129888282333499665642220178659408192689320746099638078367,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3047.725320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.33854449545343394893731571420009481696230070827795020728658244038480415289766","seed":33854449545343394893731571420009481696230070827795020728658244038480415289766,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2157.264985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.113196779278674926197509341444904337559838643849455023949753610026576743445519","seed":113196779278674926197509341444904337559838643849455023949753610026576743445519,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2723.574844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.115492331086279056611847757744217049261673748221594474863548155674575690394450","seed":115492331086279056611847757744217049261673748221594474863548155674575690394450,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2876.140988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.114241035513467823810936717921427341399223872759857113032403164638772532845701","seed":114241035513467823810936717921427341399223872759857113032403164638772532845701,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3093.603256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.66065564839168847785572520798234787146638110914359750444097932748333200838621","seed":66065564839168847785572520798234787146638110914359750444097932748333200838621,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2568.852915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.46253124217493589113809062821594863513624937918164522770725494995971025517507","seed":46253124217493589113809062821594863513624937918164522770725494995971025517507,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2739.325624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.54358257783501162395839142815009230202617198813658144528880770498543487497379","seed":54358257783501162395839142815009230202617198813658144528880770498543487497379,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2946.164424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.47192548093674967266066527945329650295575917014036986092864800461134020098956","seed":47192548093674967266066527945329650295575917014036986092864800461134020098956,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3226.112657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.98148678864232930126704950858740036428181975388020812608126393210638651554789","seed":98148678864232930126704950858740036428181975388020812608126393210638651554789,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2731.859914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.77740160127741697043671063910570383195959376704829862999132643865905746864558","seed":77740160127741697043671063910570383195959376704829862999132643865905746864558,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2283.971950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.65401953904783977727847586654677217955256110222688366928133877696101110557825","seed":65401953904783977727847586654677217955256110222688366928133877696101110557825,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2851.816720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.104338469084955173496775235212518189029657605527685624433153674690074548943171","seed":104338469084955173496775235212518189029657605527685624433153674690074548943171,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2694.719635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.9145351064817265025994047233433006503684304479884740380789079775561402504015","seed":9145351064817265025994047233433006503684304479884740380789079775561402504015,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3643.916230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.14494652022080441383225429369398692830032462330472645073837028557844963952519","seed":14494652022080441383225429369398692830032462330472645073837028557844963952519,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3213.671280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.26861778416131635982343597850211515121758568562605897213473274615829293977534","seed":26861778416131635982343597850211515121758568562605897213473274615829293977534,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2469.297640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.101581179814632001762134814705898435714752385377300699114288774590712534722443","seed":101581179814632001762134814705898435714752385377300699114288774590712534722443,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3360.201394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.35945038859636609620469501521235614716425737589952323628991053259640235554174","seed":35945038859636609620469501521235614716425737589952323628991053259640235554174,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3098.654944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.66842518611165355360106414834200542489817956877685955075955365956454528341346","seed":66842518611165355360106414834200542489817956877685955075955365956454528341346,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2672.378240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.88435454351794578474587478069306325123863359730856897111385297348826874827112","seed":88435454351794578474587478069306325123863359730856897111385297348826874827112,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3532.321563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1323529898773794312992124041451658227161106823199265821124792799097481400295","seed":1323529898773794312992124041451658227161106823199265821124792799097481400295,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2805.384460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.30837230829404486128630786638071718875239607347294293646064424816858577047322","seed":30837230829404486128630786638071718875239607347294293646064424816858577047322,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3400.442094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.7572988357665269314780746781355035217823671546310989319319515904520208494766","seed":7572988357665269314780746781355035217823671546310989319319515904520208494766,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2925.475405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.36896404851803659835278910401397997008711542872327730570494576372320089007373","seed":36896404851803659835278910401397997008711542872327730570494576372320089007373,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3051.412360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075454755884086431354379233700012508085549520773824965615300314518405430886","seed":2075454755884086431354379233700012508085549520773824965615300314518405430886,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3007.581889 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.106621009478311761455831376370525316913295276993729031655062080377522096461474","seed":106621009478311761455831376370525316913295276993729031655062080377522096461474,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3202.900060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.8755550689663126117020388615221442609577899713092230426126330681268435036965","seed":8755550689663126117020388615221442609577899713092230426126330681268435036965,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3079.777908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.95066594085552974420677903031154941499414822612501299750133596426463087030377","seed":95066594085552974420677903031154941499414822612501299750133596426463087030377,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2963.969448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.47180997114131877471206721437495807912347565438017128521132308689762568252673","seed":47180997114131877471206721437495807912347565438017128521132308689762568252673,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2927.289966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.98603787755708602650112336850494433260301776989041151276487426812993188888993","seed":98603787755708602650112336850494433260301776989041151276487426812993188888993,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3518.293734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.81184617675100533642451066091516218731538675176829758221477610705606935900900","seed":81184617675100533642451066091516218731538675176829758221477610705606935900900,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2916.889472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.114603171951359949222703798079353820271679313768694647850300135713090692233702","seed":114603171951359949222703798079353820271679313768694647850300135713090692233702,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2663.853814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.67325915610168686112529417051714861950957245218600871436628562467248807142301","seed":67325915610168686112529417051714861950957245218600871436628562467248807142301,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3101.807998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.84005533979036340615865212916968966331677958201794110922161695822215160719428","seed":84005533979036340615865212916968966331677958201794110922161695822215160719428,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3113.515088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.62287602313294266755244596756540340420204211361015573190885720307619812576125","seed":62287602313294266755244596756540340420204211361015573190885720307619812576125,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2670.232552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.109311506681815960072303611720032837316581626219155561110786054713509675483465","seed":109311506681815960072303611720032837316581626219155561110786054713509675483465,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3104.470484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.81351735883778001510477644473332057851392651486604154377356557880640596947802","seed":81351735883778001510477644473332057851392651486604154377356557880640596947802,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3290.138250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697029827398451375653062470204043759362397256876444587030294926970405717531","seed":1697029827398451375653062470204043759362397256876444587030294926970405717531,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2979.815105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.76371374024087098365585932128107282487094767818183397374907468267517532908454","seed":76371374024087098365585932128107282487094767818183397374907468267517532908454,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2609.405078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.88678188396628225708612889269443481026185218295866547307026148553323155930947","seed":88678188396628225708612889269443481026185218295866547307026148553323155930947,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2719.797668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.80158086367838871555479434868226386986954705728607293035321015201325686426378","seed":80158086367838871555479434868226386986954705728607293035321015201325686426378,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2496.115628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.94972060934563732129286097748187452338151754063850004068256169151244267162464","seed":94972060934563732129286097748187452338151754063850004068256169151244267162464,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2544.529878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.38509270740174026326483753239039714791662220903014830461680309146892274498647","seed":38509270740174026326483753239039714791662220903014830461680309146892274498647,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3080.032156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.64552373752113917292541959901828027246603467251589799284537765904016091935034","seed":64552373752113917292541959901828027246603467251589799284537765904016091935034,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3356.584534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.65640032641031565856742717192372911306263618460150591681085835943717302015344","seed":65640032641031565856742717192372911306263618460150591681085835943717302015344,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2699.835250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.73984463788192440041949350832483377441363603115371124930992508568484177532479","seed":73984463788192440041949350832483377441363603115371124930992508568484177532479,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2915.225435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.114003367582749130599232326107284202117556682540133732077394410331861237696049","seed":114003367582749130599232326107284202117556682540133732077394410331861237696049,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2673.608008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.51381029666327911379322928005760455247311111186827189828262546833323780634906","seed":51381029666327911379322928005760455247311111186827189828262546833323780634906,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3224.490248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.64463357062133903666343801956492144177708624461032860994387125848531031595927","seed":64463357062133903666343801956492144177708624461032860994387125848531031595927,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2452.191340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.45852081254889269972097482812820873792559110665664685307788323401048017303414","seed":45852081254889269972097482812820873792559110665664685307788323401048017303414,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2641.933080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.99530596940711969404421094590677512514828688070596971166124952307459404802325","seed":99530596940711969404421094590677512514828688070596971166124952307459404802325,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2904.332617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.60579371498624936599428369680022274254868330677270872565829467160751039959721","seed":60579371498624936599428369680022274254868330677270872565829467160751039959721,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3027.530766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.92040054208613154126120876807283776565584019002729358207414691435346773268344","seed":92040054208613154126120876807283776565584019002729358207414691435346773268344,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2957.189492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.60683630405525593974092410476965198352202887444739137464473606348484902831454","seed":60683630405525593974092410476965198352202887444739137464473606348484902831454,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3017.446731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.27151589545587358968307502504361563680855213679985912072552777753753551236036","seed":27151589545587358968307502504361563680855213679985912072552777753753551236036,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2840.976470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.91587556566251016501549969531583171920052368084412598973418791833565082411926","seed":91587556566251016501549969531583171920052368084412598973418791833565082411926,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3072.358897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4145376902816235767374035207638418352371460357883283886309669647925078795149","seed":4145376902816235767374035207638418352371460357883283886309669647925078795149,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2950.397514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.65855154194520628959800573385422997214329114797533423132991737968227406352216","seed":65855154194520628959800573385422997214329114797533423132991737968227406352216,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3082.031547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.104475785129660372453333415882150004376226524527619148953143513297778568684857","seed":104475785129660372453333415882150004376226524527619148953143513297778568684857,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3041.772204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.80224713182216869770158154881300716029318213406810994603364119265082716941435","seed":80224713182216869770158154881300716029318213406810994603364119265082716941435,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2874.748206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.16310393994988690468003259507477191308165210230315320059372485811159277901666","seed":16310393994988690468003259507477191308165210230315320059372485811159277901666,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31456) { a_addr: 'h105a4  a_data: 'hb884a056  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h1b65d  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1987.467728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.6767427630821267764518941990178026807221358206476331159738604437777532036103","seed":6767427630821267764518941990178026807221358206476331159738604437777532036103,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34084) { a_addr: 'h105bc  a_data: 'hff764673  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h18614  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2132.787833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.63489071977741251749842502622331758290315637857018453911733091419572286555544","seed":63489071977741251749842502622331758290315637857018453911733091419572286555544,"line":224,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31516) { a_addr: 'h10370  a_data: 'hffb1bc08  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h19e02  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2502.040645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.32463588574085390948626979825231557661332045642497999774644057237709369630729","seed":32463588574085390948626979825231557661332045642497999774644057237709369630729,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@38718) { a_addr: 'h105e0  a_data: 'h39b9e872  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19265  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2611.754582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.31708399428421437264470493027571451425944726962991403816017689484675707854090","seed":31708399428421437264470493027571451425944726962991403816017689484675707854090,"line":224,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31688) { a_addr: 'h1040c  a_data: 'h88070bb3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h18dd6  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2063.178520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.58579120933541082361332509717717425450735441945514132720727791120927497514007","seed":58579120933541082361332509717717425450735441945514132720727791120927497514007,"line":218,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@192894) { a_addr: 'h106ac  a_data: 'h7c536278  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1aecf  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3114.368080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.14178655663723786955098113403273124056159634273734068715264351438551211190110","seed":14178655663723786955098113403273124056159634273734068715264351438551211190110,"line":222,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34026) { a_addr: 'h10704  a_data: 'ha39e9295  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h19552  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2248.928808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.57424181098320500488154399149700009600059606930375775095168360499550287570160","seed":57424181098320500488154399149700009600059606930375775095168360499550287570160,"line":223,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@94722) { a_addr: 'h10448  a_data: 'hbe1a86d0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1a9a8  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3260.006725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.49210897344730316462192678451644662181825767639039042206672413566873718390462","seed":49210897344730316462192678451644662181825767639039042206672413566873718390462,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33014) { a_addr: 'h10710  a_data: 'h77ac888a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1bd5a  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1799.622212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.26727501857656055656908018001265046253783055428236290600532112605934292985064","seed":26727501857656055656908018001265046253783055428236290600532112605934292985064,"line":222,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33434) { a_addr: 'h106d4  a_data: 'h9f1e8884  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h1aea5  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2765.257796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.51413825869382223540881736635117406443503673605732927798433550683089926131232","seed":51413825869382223540881736635117406443503673605732927798433550683089926131232,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31556) { a_addr: 'h1043c  a_data: 'h226e95cd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1b196  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2488.760062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.76637365325781003701192512480574723547375917470540036501900958506864559762289","seed":76637365325781003701192512480574723547375917470540036501900958506864559762289,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33854) { a_addr: 'h107dc  a_data: 'h858d1a05  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1bd46  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2497.742514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.50432128139341546883294615993464043668287892896226332018527919299734803336903","seed":50432128139341546883294615993464043668287892896226332018527919299734803336903,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@37556) { a_addr: 'h10384  a_data: 'h4cbf32f5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h1b6da  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2244.736994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.19750443390770675514265694873028499682719465896575950605390885389328595030169","seed":19750443390770675514265694873028499682719465896575950605390885389328595030169,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@41550) { a_addr: 'h107ac  a_data: 'h487aff6e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1a9c3  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1839.490000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.63745860596306515117507857354617976663429609519288396569517959273023556835299","seed":63745860596306515117507857354617976663429609519288396569517959273023556835299,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32064) { a_addr: 'h10444  a_data: 'h57ccaf86  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1b1dd  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2484.222775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.7169364012275549095009313103659037854307751395125754747510098936586871310929","seed":7169364012275549095009313103659037854307751395125754747510098936586871310929,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32798) { a_addr: 'h10518  a_data: 'h17bacfb2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1a2ea  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2221.544250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.111874741212827796931435903202590945976601465767278820387807139498722422254078","seed":111874741212827796931435903202590945976601465767278820387807139498722422254078,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31968) { a_addr: 'h10368  a_data: 'h3822b79b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1ae52  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2275.539422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.47822858500114774219443822963415142855373007503853432363733208049491130685738","seed":47822858500114774219443822963415142855373007503853432363733208049491130685738,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32136) { a_addr: 'h106d0  a_data: 'hbc01f657  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h1a224  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2242.404946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.4444995197261739184944136300543103990868708587198576869099341124953955454636","seed":4444995197261739184944136300543103990868708587198576869099341124953955454636,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35556) { a_addr: 'h105d0  a_data: 'h1ce2a928  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h1ae39  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2154.156077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.6246341824052561357307118548260176168865158567871337869690654341378318841","seed":6246341824052561357307118548260176168865158567871337869690654341378318841,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33420) { a_addr: 'h10620  a_data: 'hfc18b9fb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h18613  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2411.113408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.12043347308360464489900602040639327522935746713561870404743549419586363270396","seed":12043347308360464489900602040639327522935746713561870404743549419586363270396,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36846) { a_addr: 'h10364  a_data: 'ha5abf3b5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h1b61a  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2740.981458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.81829135718627574396672094347695422765215234245140054609934514107033090830378","seed":81829135718627574396672094347695422765215234245140054609934514107033090830378,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33356) { a_addr: 'h106b0  a_data: 'he579cffb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h1920c  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1730.367529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.27524763760595915020018572065893910797676423834479979485012854011702939491831","seed":27524763760595915020018572065893910797676423834479979485012854011702939491831,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35994) { a_addr: 'h104b8  a_data: 'h39e20199  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h18dfe  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2062.136154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.11601980505716067947506694461672014615862018862460643808053018718301315823742","seed":11601980505716067947506694461672014615862018862460643808053018718301315823742,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31720) { a_addr: 'h107a8  a_data: 'h36ddb24f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h1a50f  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2522.919703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.61478237511331893846405714239830993835518610279398722523742014985332386985178","seed":61478237511331893846405714239830993835518610279398722523742014985332386985178,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@44168) { a_addr: 'h107d0  a_data: 'h865ea9e4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1a51a  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2177.325652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.16589709450074453504198696864200433753468877540542781488045087902221192151321","seed":16589709450074453504198696864200433753468877540542781488045087902221192151321,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35406) { a_addr: 'h10790  a_data: 'h9630b53  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h18d80  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1866.812925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.85156431107692271135765859612533034200821118480638489250182478713022895644411","seed":85156431107692271135765859612533034200821118480638489250182478713022895644411,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32294) { a_addr: 'h10414  a_data: 'hbec60ea6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1bdb5  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1825.837475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.23280342609519261306719592660915133460248383414986037249954876956394455912671","seed":23280342609519261306719592660915133460248383414986037249954876956394455912671,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31456) { a_addr: 'h107c0  a_data: 'h3e6d0c91  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h181f1  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2722.222162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.104816954937012339687343042953464712254065646119221844369109793008773517963137","seed":104816954937012339687343042953464712254065646119221844369109793008773517963137,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34090) { a_addr: 'h105a4  a_data: 'h31908408  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1b66b  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2817.636312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.97797827689426718416350957743425270234847247508866352084029686715822726799053","seed":97797827689426718416350957743425270234847247508866352084029686715822726799053,"line":217,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40914) { a_addr: 'h106fc  a_data: 'h837d2683  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h1a2a1  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1980.052500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.39964362455229974177339904238848441630764129870395408466411918822770773243480","seed":39964362455229974177339904238848441630764129870395408466411918822770773243480,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3361.909659 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.72536354479991780340146545081119534502197837814935375330128421098209947992758","seed":72536354479991780340146545081119534502197837814935375330128421098209947992758,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3251.602206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.68937052949959854560379136876973504551252625938806205206991785625530096560848","seed":68937052949959854560379136876973504551252625938806205206991785625530096560848,"line":343,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3901.659210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.55614540328788100992778719231119360673799210738289208694908928965053730620154","seed":55614540328788100992778719231119360673799210738289208694908928965053730620154,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=3080289) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.50389252725262763035030782486810383107218701285643627761535191869254910194491","seed":50389252725262763035030782486810383107218701285643627761535191869254910194491,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=280869) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.51592991347872151431865811962519752974951601977285598798398796644147556032405","seed":51592991347872151431865811962519752974951601977285598798398796644147556032405,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.99222698597857480076586085576671597019579546681893178006560233414343981916052","seed":99222698597857480076586085576671597019579546681893178006560233414343981916052,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3677745832152294798161170245633075469061768910034965768912281803266537974453","seed":3677745832152294798161170245633075469061768910034965768912281803266537974453,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.23292548715752848710183718230496679746801717313876960299321187408453369451974","seed":23292548715752848710183718230496679746801717313876960299321187408453369451974,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.77278212158764329798439234593612260329785984522982240721830871371084928354138","seed":77278212158764329798439234593612260329785984522982240721830871371084928354138,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=296808) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=272795) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=272363) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.15215258607373167559756539216708348519320024715400897896215100447240616803260","seed":15215258607373167559756539216708348519320024715400897896215100447240616803260,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.82846559542197463998535359295707563648242275108898704042403317483017422950328","seed":82846559542197463998535359295707563648242275108898704042403317483017422950328,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.34161832245862045967364952349516900909372684241485617335691967065273794173315","seed":34161832245862045967364952349516900909372684241485617335691967065273794173315,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.68609528451146670824986061338086674647670348734174615680665799189382258387387","seed":68609528451146670824986061338086674647670348734174615680665799189382258387387,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.15012679523246385902245917589269560118245125790398165045555756303877320249631","seed":15012679523246385902245917589269560118245125790398165045555756303877320249631,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.39520742215261295319076225368663300420321423132724633550168674938594262194211","seed":39520742215261295319076225368663300420321423132724633550168674938594262194211,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.109840635823581331353293941254131708900525022447266282560886010678174237945054","seed":109840635823581331353293941254131708900525022447266282560886010678174237945054,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.115044919026951478553240340227602556027439584065854215393682704080109511022420","seed":115044919026951478553240340227602556027439584065854215393682704080109511022420,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.37063138186091678606776019800763567076490061479075756070593716613851881459048","seed":37063138186091678606776019800763567076490061479075756070593716613851881459048,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.105349015713468326411637015246590253508425534186077109683641918744123520636663","seed":105349015713468326411637015246590253508425534186077109683641918744123520636663,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.67684230358645931486503160653206906376287086884506571171944971027311818222138","seed":67684230358645931486503160653206906376287086884506571171944971027311818222138,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.13308193064351528659268440985216373823713507848714729885388809221561856188996","seed":13308193064351528659268440985216373823713507848714729885388809221561856188996,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.60501675024194394789730576167461093532656275129197516556992614070724824980940","seed":60501675024194394789730576167461093532656275129197516556992614070724824980940,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1294502592987456923470177753129960960493525354123100705569207214939788831934","seed":1294502592987456923470177753129960960493525354123100705569207214939788831934,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.63470813600793640684411038021570520382798283452277388370138819561664515200661","seed":63470813600793640684411038021570520382798283452277388370138819561664515200661,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.42646847478381721462887409835485486066378088582657141692788458276067477517458","seed":42646847478381721462887409835485486066378088582657141692788458276067477517458,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.51193731885561816136790404442688900923204040078058532671596054860400624785191","seed":51193731885561816136790404442688900923204040078058532671596054860400624785191,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.86735622954034166539396096196289607959065294246130143410303294955588479064202","seed":86735622954034166539396096196289607959065294246130143410303294955588479064202,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.104218516375905988019288160113477528532624226102477816652032515998405749979345","seed":104218516375905988019288160113477528532624226102477816652032515998405749979345,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.84694130060691388055358259663591694988346138923188394481677257240881155727861","seed":84694130060691388055358259663591694988346138923188394481677257240881155727861,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.43915856724206536737607838274716922847750853994275651267700811315896024524231","seed":43915856724206536737607838274716922847750853994275651267700811315896024524231,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.89317041100970421322276154691056970238558220392515660471741251740886397905908","seed":89317041100970421322276154691056970238558220392515660471741251740886397905908,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.70827557314190073224760252368406893902334381397026027316513255832256939368718","seed":70827557314190073224760252368406893902334381397026027316513255832256939368718,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.53210112295863161702164021145934567870223350652899122569336905726583706052901","seed":53210112295863161702164021145934567870223350652899122569336905726583706052901,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted_sim_dv' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.81516448321264515161005767307122863905113636589618661058501900567004343741872","seed":81516448321264515161005767307122863905113636589618661058501900567004343741872,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=265180) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=264787) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=268093) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.58972783124364343557059391195203827664446495191944245410788128527845619795464","seed":58972783124364343557059391195203827664446495191944245410788128527845619795464,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=401964) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.60397056698154289351481798698683237335207072431389307821166799762771561743359","seed":60397056698154289351481798698683237335207072431389307821166799762771561743359,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.43262267176117780308460176321920913823497077683066377624112629788659840456189","seed":43262267176117780308460176321920913823497077683066377624112629788659840456189,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.97588057414741734647394193392755375943496288678818082746770613647357937004411","seed":97588057414741734647394193392755375943496288678818082746770613647357937004411,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.40065476749744994824070358458577595397210622433332302767940941832677962157821","seed":40065476749744994824070358458577595397210622433332302767940941832677962157821,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.88665004957596531521893288414021251604102715360129028853339181961737481590477","seed":88665004957596531521893288414021251604102715360129028853339181961737481590477,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:22:10: //hw/bitstream/hyperdebug:mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.23066361500756507496218898697536913146985294440854089057137508616322343885761","seed":23066361500756507496218898697536913146985294440854089057137508616322343885761,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["\tFile \"/nightly/current_run/opentitan/rules/bitstreams.bzl\", line 77, column 13, in _bitstreams_repo_impl\n","\t\tfail(\"Bitstream cache not initialized properly.\")\n","Error in fail: Bitstream cache not initialized properly.\n","ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: /nightly/current_run/opentitan/hw/bitstream/hyperdebug/BUILD:10:10: //hw/bitstream/hyperdebug:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_hyperdebug_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.\n","ERROR: Analysis of target '//sw/device/examples/sram_program:sram_program' failed; build aborted: Analysis failed\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.101688734402139651884584026099812591640776541591020946065133060979700046065543","seed":101688734402139651884584026099812591640776541591020946065133060979700046065543,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=273807) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=294464) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=295193) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.67958431209182439379672629802212341651320960660702211798692640824192041244327","seed":67958431209182439379672629802212341651320960660702211798692640824192041244327,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=265071) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=267487) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=271358) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.104300252799385344753975033786342335045125398668593398997557463682551318692812","seed":104300252799385344753975033786342335045125398668593398997557463682551318692812,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=268093) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=265071) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=267487) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.41808255464964538955238886495668582417357738237805725554341703472585327174328","seed":41808255464964538955238886495668582417357738237805725554341703472585327174328,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.109428265983069528347300869636966509496246472777633199737029913377503610916724","seed":109428265983069528347300869636966509496246472777633199737029913377503610916724,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.94745419614159170496346739956701773798185248401060778764713225022473878519384","seed":94745419614159170496346739956701773798185248401060778764713225022473878519384,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.79809702058530776060380193412405990268763106271426575071704333605725691850793","seed":79809702058530776060380193412405990268763106271426575071704333605725691850793,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.112798731093656167824161961211668489543133759775240398609518892637159055738565","seed":112798731093656167824161961211668489543133759775240398609518892637159055738565,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.13335029585208251734393627423747902046341655715825595699638945284523481671761","seed":13335029585208251734393627423747902046341655715825595699638945284523481671761,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=410799) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.48567461982676841513637414039179897479337212341804859726846388353586617509064","seed":48567461982676841513637414039179897479337212341804859726846388353586617509064,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=301851) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=301343) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=306940) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.22540236397109950455142129353539096461166399384976532741116676269722275297767","seed":22540236397109950455142129353539096461166399384976532741116676269722275297767,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=275174) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=291734) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=292723) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.99278777663022523926284711717049602368947979951116680283166408149182534051135","seed":99278777663022523926284711717049602368947979951116680283166408149182534051135,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["\n","Waiting for it to complete...\n","Another command (pid=273542) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.100692013152855411093317796506555528988888641435094818620122405362692426645441","seed":100692013152855411093317796506555528988888641435094818620122405362692426645441,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=758330) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.89440805811873542566320210427514995291156086084954100765990440977741490452036","seed":89440805811873542566320210427514995291156086084954100765990440977741490452036,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=307783) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=309833) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=304287) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.62238028909715979367520308603521501198312304300782175879861845494843438759320","seed":62238028909715979367520308603521501198312304300782175879861845494843438759320,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.99825354416964346975572382844006976928398010846062018500893155019165263553434","seed":99825354416964346975572382844006976928398010846062018500893155019165263553434,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.72537246074041500947350486861688586416151994190557107167878685800036857489259","seed":72537246074041500947350486861688586416151994190557107167878685800036857489259,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.2800082037284827057380579878701131987086708448118096867856959655209587422600","seed":2800082037284827057380579878701131987086708448118096867856959655209587422600,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=411960) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.14752263055175744907242613474013408046008581102134494923144005515292463306689","seed":14752263055175744907242613474013408046008581102134494923144005515292463306689,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=327396) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=310796) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=323981) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.92637370744136710822711202617324109780526313363295365100784986140649423004838","seed":92637370744136710822711202617324109780526313363295365100784986140649423004838,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=270577) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=282356) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=307783) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.16976275309446434401582874108850299578548343916431584960592590836471712582805","seed":16976275309446434401582874108850299578548343916431584960592590836471712582805,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=272795) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=272363) is running. Waiting for it to complete on the server (server_pid=264734)...\n","Another command (pid=293698) is running. Waiting for it to complete on the server (server_pid=264734)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.85094698488767226563235986970977445589042514970712089254502684383013103482311","seed":85094698488767226563235986970977445589042514970712089254502684383013103482311,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.91221999381544225257010854248354705975961542949219950825535318276822214209588","seed":91221999381544225257010854248354705975961542949219950825535318276822214209588,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.71402255776312892405329177451387275209979085050921572751760011590475483569830","seed":71402255776312892405329177451387275209979085050921572751760011590475483569830,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.37787006725151486226824322199200085902846049031875093934134351981786334372864","seed":37787006725151486226824322199200085902846049031875093934134351981786334372864,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.9568703498477683150808116559461782983611803547419942168623389427274533671846","seed":9568703498477683150808116559461782983611803547419942168623389427274533671846,"line":235,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 5483.691609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.51499707672022069839314406853093510277885413345611426146033511964421758329952","seed":51499707672022069839314406853093510277885413345611426146033511964421758329952,"line":225,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 4169.007348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.19880708378407417465844940235419125197911871945549190953713281396781128686577","seed":19880708378407417465844940235419125197911871945549190953713281396781128686577,"line":236,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 5279.171040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.65950786331304228499471889776481839419457095805961363346835103389909355500246","seed":65950786331304228499471889776481839419457095805961363346835103389909355500246,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3616.411000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"1.chip_sw_power_idle_load.19628231410697902712491367026121464204569376678972667098957984073618251535915","seed":19628231410697902712491367026121464204569376678972667098957984073618251535915,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 2978.795000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"2.chip_sw_power_idle_load.52537227927588874369250009529195742340256431164098168692696366987114208633868","seed":52537227927588874369250009529195742340256431164098168692696366987114208633868,"line":312,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 3409.395000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.2126243898115194783530637251170058907084843317467872376341665889281086028","seed":2126243898115194783530637251170058907084843317467872376341665889281086028,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3375.912000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"1.chip_sw_power_sleep_load.39100792765251240536138658678967845795518496682557150538751471365944225377291","seed":39100792765251240536138658678967845795518496682557150538751471365944225377291,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3521.717000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.5789739485064185471034546018765128924328665495965077180104155451427920309083","seed":5789739485064185471034546018765128924328665495965077180104155451427920309083,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3576.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.20242249615054159556603765477439473115208987657682640358754482505193569763312","seed":20242249615054159556603765477439473115208987657682640358754482505193569763312,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11734.736636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.49359680872014447099083115173722270890721730989268342008271145959000804965385","seed":49359680872014447099083115173722270890721730989268342008271145959000804965385,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 10033.849285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.5566169083191990364024608408960169117029581292088733757942365384806847552458","seed":5566169083191990364024608408960169117029581292088733757942365384806847552458,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 13507.709327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.16193490153248483663173200595531001691120811066357946199484447897641178281166","seed":16193490153248483663173200595531001691120811066357946199484447897641178281166,"line":272,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.69439725076184699103824995858190929033147728507896681900944951026342186002911","seed":69439725076184699103824995858190929033147728507896681900944951026342186002911,"line":272,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.46757814971136312716073300884592334217214476727453128102306324850054542548933","seed":46757814971136312716073300884592334217214476727453128102306324850054542548933,"line":272,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds":[{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.99805937912832585794014478807324513780787539095850957539215000867298878707067","seed":99805937912832585794014478807324513780787539095850957539215000867298878707067,"line":318,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["UVM_INFO @ 4337.767713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*])":[{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.23034514429600466364264018214703459891366329242374467566474271033667152207248","seed":23034514429600466364264018214703459891366329242374467566474271033667152207248,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["UVM_INFO @ 4172.360370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.109011948260975135803958027642692101792431117586907466206961693522312038454008","seed":109011948260975135803958027642692101792431117586907466206961693522312038454008,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5055.687992 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5055.687992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.34651396661123833552225386053789745829708893865938194260804915047320063950705","seed":34651396661123833552225386053789745829708893865938194260804915047320063950705,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 3818.949580 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 3818.949580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.85090896432089311102267316491620157102954895388353884121029923996806555921770","seed":85090896432089311102267316491620157102954895388353884121029923996806555921770,"line":327,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5140.981516 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5140.981516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.63295171402325898061001974665810627054528001083094035857367710098905332422737","seed":63295171402325898061001974665810627054528001083094035857367710098905332422737,"line":307,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3791.276324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_no_meas.77689855863466981840535016555508591710689154741500025985245929631124476254898","seed":77689855863466981840535016555508591710689154741500025985245929631124476254898,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 16223.662651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_no_meas.42510581606371853747675075115475785288330546363569299009890749844181932737485","seed":42510581606371853747675075115475785288330546363569299009890749844181932737485,"line":319,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 15935.613159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]":[{"name":"chip_sw_sleep_pin_mio_dio_val","qual_name":"2.chip_sw_sleep_pin_mio_dio_val.103874128442502953162503351368580999748605248644871044533645517451643647398313","seed":103874128442502953162503351368580999748605248644871044533645517451643647398313,"line":451,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log","log_context":["UVM_INFO @ 2902.765000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"5.chip_sw_all_escalation_resets.57739784261681001166159348458136824830434994678197113609369740323149026782339","seed":57739784261681001166159348458136824830434994678197113609369740323149026782339,"line":321,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2972.616906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"37.chip_sw_all_escalation_resets.110873158499068557164705453565759433408530414831840433023250292639048821610580","seed":110873158499068557164705453565759433408530414831840433023250292639048821610580,"line":316,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2731.494040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.97161211543898082719305134543689152052630017562486121151218134277880728119448","seed":97161211543898082719305134543689152052630017562486121151218134277880728119448,"line":321,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2849.340816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"70.chip_sw_all_escalation_resets.94409096418771745732563437422331274407545549307511286343123321059614097924759","seed":94409096418771745732563437422331274407545549307511286343123321059614097924759,"line":321,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3741.930452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"36.chip_sw_all_escalation_resets.60548001256610109402352899582232133462553029314166051418303337533167515650902","seed":60548001256610109402352899582232133462553029314166051418303337533167515650902,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2705.565495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"74.chip_sw_all_escalation_resets.34141095195338908916732907261466200091966650155308962256139409643127265255954","seed":34141095195338908916732907261466200091966650155308962256139409643127265255954,"line":322,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3310.321454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"84.chip_sw_all_escalation_resets.35727729650625846091817958511457141631257006810748214353020359261216442507563","seed":35727729650625846091817958511457141631257006810748214353020359261216442507563,"line":317,"log_path":"/nightly/current_run/scratch/reseed_opt/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2986.001523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1724,"total":2008,"percent":85.85657370517929}