{"block":{"name":"pattgen","variant":null,"commit":"32edacb68e9a736ae5909ca16949f5c4ce181520","commit_short":"32edacb","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/32edacb68e9a736ae5909ca16949f5c4ce181520","revision_info":"GitHub Revision: [`32edacb`](https://github.com/lowrisc/opentitan/tree/32edacb68e9a736ae5909ca16949f5c4ce181520)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-24T04:19:36Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":7.0,"sim_time":164.94984,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.363913,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":19.631395,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":3.0,"sim_time":289.825657,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":23.046419999999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":23.930627,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":19.631395,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":23.046419999999998,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":63,"total":63,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3602.063504012301,"sim_time":0.0,"passed":30,"total":50,"percent":60.0}},"passed":30,"total":50,"percent":60.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":79.0,"sim_time":2634.106806,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":35.778019,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10802.074475919828,"sim_time":0.0,"passed":27,"total":50,"percent":54.0}},"passed":27,"total":50,"percent":54.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":19.627321,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":15.343932,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":42.285863,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":42.285863,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.363913,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":19.631395,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":23.046419999999998,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":32.889674,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.363913,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":19.631395,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":23.046419999999998,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":32.889674,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":214,"total":257,"percent":83.26848249027238},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":101.89064200000001,"passed":25,"total":25,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":252.620506,"passed":5,"total":5,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":101.89064200000001,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":114.0,"sim_time":8844.642544,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":180.0,"sim_time":10026.738972,"passed":33,"total":50,"percent":66.0}},"passed":33,"total":50,"percent":66.0}},"passed":33,"total":50,"percent":66.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.84810049466245822047150150782470312345474048653624257216262566695837190146628","seed":84810049466245822047150150782470312345474048653624257216262566695837190146628,"line":165,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1021045452 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1021045452 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1021117615 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.114985388203968144341287311921576223525809716612056667277104816950549467648007","seed":114985388203968144341287311921576223525809716612056667277104816950549467648007,"line":179,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2314160098 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2314160098 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2314368428 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.79329369439331327297164664361621061112679543346163997945371484771386277730490","seed":79329369439331327297164664361621061112679543346163997945371484771386277730490,"line":171,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 447530472 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 447530472 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 447613808 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.2174382146958929141705515290119967513863667423105588388360102500068717952949","seed":2174382146958929141705515290119967513863667423105588388360102500068717952949,"line":187,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2699789930 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2699789930 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2699909930 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.27394200117382806010069434917257725662052342064992237422717327082443840419368","seed":27394200117382806010069434917257725662052342064992237422717327082443840419368,"line":150,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5591735384 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5591735384 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 5591957608 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.76590200605903451445618950379335966877102555636183824003278100038324162861541","seed":76590200605903451445618950379335966877102555636183824003278100038324162861541,"line":117,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1538111626 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1538111626 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1538403295 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.59696852023585857480158560139764663429506420336048648332163999997285497545835","seed":59696852023585857480158560139764663429506420336048648332163999997285497545835,"line":278,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8613905855 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 8613905855 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 8614072523 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.104924475840416142465365374677586273116828886406525097038722696215515931180649","seed":104924475840416142465365374677586273116828886406525097038722696215515931180649,"line":124,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1694535148 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1694535148 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1694682685 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.88957284597063821982181141904548971278384022167879596627280544632376014922579","seed":88957284597063821982181141904548971278384022167879596627280544632376014922579,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2571727622 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2571727622 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 2572047622 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.73874173228510907537470327620236515810286890420935448597275920736003687015981","seed":73874173228510907537470327620236515810286890420935448597275920736003687015981,"line":254,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4925953199 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4925953199 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 4926078200 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.11917442699816072331713957417120073598020560243680156619320278353924226063787","seed":11917442699816072331713957417120073598020560243680156619320278353924226063787,"line":140,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1053985728 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1053985728 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1054087179 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.108082441597164292056439722190205715017998249241072660716596830708978507406542","seed":108082441597164292056439722190205715017998249241072660716596830708978507406542,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 569073183 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 569073183 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 569364852 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.55961081013625359111064555946755817369680384732331714019178304689500819037390","seed":55961081013625359111064555946755817369680384732331714019178304689500819037390,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 207880322 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 207880322 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 208000322 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.22679469224676611696686565605048984243495809339002486078492310270214227339000","seed":22679469224676611696686565605048984243495809339002486078492310270214227339000,"line":163,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3972189622 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3972189622 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 3972339622 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.42589165609411468175714352891731778930435178450947865450950148952447170634861","seed":42589165609411468175714352891731778930435178450947865450950148952447170634861,"line":213,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4252024740 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4252024740 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 4252117764 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.31335360687967727938471901479058836726156936790886890981225442577657267714938","seed":31335360687967727938471901479058836726156936790886890981225442577657267714938,"line":165,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2750852238 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2750852238 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 2751212238 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.1221985822190466875052238763665304834533707710830760426060417080347118859266","seed":1221985822190466875052238763665304834533707710830760426060417080347118859266,"line":214,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2187892418 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2187892418 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2188055682 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.29117609987044524442937667417176977896784549724306715022615065611603988970812","seed":29117609987044524442937667417176977896784549724306715022615065611603988970812,"line":117,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 670396877 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 670396877 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 670476877 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.62413700903380124891992049411635829873908013097500683519428821362036223636924","seed":62413700903380124891992049411635829873908013097500683519428821362036223636924,"line":117,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 698900875 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 698900875 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 698930875 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.28980368665567869573287995842315249400509643097248106885548396703261462019236","seed":28980368665567869573287995842315249400509643097248106885548396703261462019236,"line":257,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2003582561 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2003582561 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2003644415 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.8551314917412662691477592139501911219413200658976304331355563814731722463243","seed":8551314917412662691477592139501911219413200658976304331355563814731722463243,"line":115,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 897447304 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 897447304 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 897627304 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.19416204449255943302676138224108834519575028431317461489418735279950593442746","seed":19416204449255943302676138224108834519575028431317461489418735279950593442746,"line":308,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1713868760 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1713868760 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 1713928760 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.26570094556676017055353745947496359224422424311671887051047463302394773143281","seed":26570094556676017055353745947496359224422424311671887051047463302394773143281,"line":114,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 874907868 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 874907868 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 875271508 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.64680669379494757567773812490378211500984783205086595485440084696372648040283","seed":64680669379494757567773812490378211500984783205086595485440084696372648040283,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 989485117 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 989485117 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 989577898 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.32317059454659367393167820076122626263432303867711829434355727868543101883552","seed":32317059454659367393167820076122626263432303867711829434355727868543101883552,"line":412,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5674112980 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5674112980 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 9/10\n","UVM_INFO @ 5674212980 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.97085109507152781815084236906268373233659352641144308305029649643139664164577","seed":97085109507152781815084236906268373233659352641144308305029649643139664164577,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 726278830 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 726278830 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 726564546 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.29166999606191717511836956596055275351792089519764389265419301660083659696097","seed":29166999606191717511836956596055275351792089519764389265419301660083659696097,"line":192,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10216255476 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 10216255476 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 10216366588 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.7589589702294260252548867858092134073411997113825759803108609738945620064146","seed":7589589702294260252548867858092134073411997113825759803108609738945620064146,"line":279,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4026077009 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4026077009 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 4026285339 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.62353478355228920587262886726410832845613932190649210383482586377081500440637","seed":62353478355228920587262886726410832845613932190649210383482586377081500440637,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1284924128 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1284924128 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1285094344 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.68367927892172409614780915660740960484670611168992219955558686751445575095451","seed":68367927892172409614780915660740960484670611168992219955558686751445575095451,"line":229,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1973185802 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1973185802 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 1973220686 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.18166976196609147916224546548089666489052239042440876775188264819998466923240","seed":18166976196609147916224546548089666489052239042440876775188264819998466923240,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2595166968 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2595166968 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2595333636 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.18994943973383171448229158029629902853555265001089160196326758039445530704901","seed":18994943973383171448229158029629902853555265001089160196326758039445530704901,"line":149,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1125275048 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1125275048 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1125367829 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.76328037018806305812165093497653500898652679391479818556212034845023117698832","seed":76328037018806305812165093497653500898652679391479818556212034845023117698832,"line":168,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2118876288 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2118876288 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 2118959620 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.59744562565800942073372186717529134275545419260962815926604378921651887346662","seed":59744562565800942073372186717529134275545419260962815926604378921651887346662,"line":124,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2946240054 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2946240054 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2946534174 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.103279327294995259565442894499095256399322039999746136498451777921621067049244","seed":103279327294995259565442894499095256399322039999746136498451777921621067049244,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4078896562 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4078896562 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 4079229895 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.39727349387607610787856598507187471077932337382581413776621415599046941786621","seed":39727349387607610787856598507187471077932337382581413776621415599046941786621,"line":186,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7573908983 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7573908983 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 7574277407 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.82948116794717485422913053171037274471310221963137697487759388024361280617848","seed":82948116794717485422913053171037274471310221963137697487759388024361280617848,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 249519561 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 249519561 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 249620571 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.109720253077536566204712342151043922477406315726079016904181628777670704839143","seed":109720253077536566204712342151043922477406315726079016904181628777670704839143,"line":214,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2971075427 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2971075427 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2971195427 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.51775159220899098017202953697108499742040803740379274875169556860895816260970","seed":51775159220899098017202953697108499742040803740379274875169556860895816260970,"line":121,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3942175207 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3942175207 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3942258541 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.109552614895309690286069640863400940572448575429986078056455255977270410712456","seed":109552614895309690286069640863400940572448575429986078056455255977270410712456,"line":118,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 686127947 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 686127947 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 686327947 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.75662873340521367745097425336821796464619080163160401453756301149383006031562","seed":75662873340521367745097425336821796464619080163160401453756301149383006031562,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1971348914 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1971348914 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1971389730 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.14399251412509816004368874616816514306991238977825232316741469486218995445382","seed":14399251412509816004368874616816514306991238977825232316741469486218995445382,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1017049055 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1017049055 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1017776327 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.111722579915402681028705298351917441918061336421348217450532005192844551602324","seed":111722579915402681028705298351917441918061336421348217450532005192844551602324,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 139442371 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 139442371 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 139544411 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.68129789027784211603408858919219755327515373479933810269101798338963944522786","seed":68129789027784211603408858919219755327515373479933810269101798338963944522786,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 205498003 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 205498003 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 205601093 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.88616827863039885657618073073177474410912627448094703577462249176322934989246","seed":88616827863039885657618073073177474410912627448094703577462249176322934989246,"line":182,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1382840419 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1382840419 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 1382960419 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.55157633984692063543778236180736083983445431857435740024110329560619429911065","seed":55157633984692063543778236180736083983445431857435740024110329560619429911065,"line":267,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1896987568 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1896987568 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 1897089019 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.104026633867055747474869561964620853630499341621831593632808359534670776636831","seed":104026633867055747474869561964620853630499341621831593632808359534670776636831,"line":167,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2353869105 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2353869105 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2354369105 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.95789807243908902716856309143638426727677405347753182789007627718782420065944","seed":95789807243908902716856309143638426727677405347753182789007627718782420065944,"line":176,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6817912444 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6817912444 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 6818329114 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"1.pattgen_stress_all.44603494650527021158874688035033151537300366024719664065994253623378367378683","seed":44603494650527021158874688035033151537300366024719664065994253623378367378683,"line":137,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11412\n"]},{"name":"pattgen_stress_all","qual_name":"4.pattgen_stress_all.22947538407215049158295687961345089714931012612141275016186566836434432942380","seed":22947538407215049158295687961345089714931012612141275016186566836434432942380,"line":150,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name Type Size Value \n","--------------------------------------\n","exp_item pattgen_item - @11391\n"]},{"name":"pattgen_stress_all","qual_name":"9.pattgen_stress_all.10139785281038199105023039159505130190766025955256881099411467773880754469280","seed":10139785281038199105023039159505130190766025955256881099411467773880754469280,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11316\n"]},{"name":"pattgen_stress_all","qual_name":"11.pattgen_stress_all.12806977382064452584010322236507712321844210115950736818994266748154788473384","seed":12806977382064452584010322236507712321844210115950736818994266748154788473384,"line":142,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name Type Size Value \n","--------------------------------------\n","exp_item pattgen_item - @11230\n"]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.63289876325770828049026126610769478607320610382348590716556725649632808728619","seed":63289876325770828049026126610769478607320610382348590716556725649632808728619,"line":151,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name Type Size Value \n","--------------------------------------\n","exp_item pattgen_item - @11297\n"]},{"name":"pattgen_stress_all","qual_name":"23.pattgen_stress_all.38136215190508147551165157220805781022985638338198046153022758220129561134962","seed":38136215190508147551165157220805781022985638338198046153022758220129561134962,"line":138,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11350\n"]},{"name":"pattgen_stress_all","qual_name":"26.pattgen_stress_all.8367883436241959415746873131499714746876899914653343664992154293393247557114","seed":8367883436241959415746873131499714746876899914653343664992154293393247557114,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11312\n"]},{"name":"pattgen_stress_all","qual_name":"29.pattgen_stress_all.62112757575900288704268932257205259687087102754431592550334079141872072118683","seed":62112757575900288704268932257205259687087102754431592550334079141872072118683,"line":140,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11249\n"]},{"name":"pattgen_stress_all","qual_name":"30.pattgen_stress_all.8512550636053661315222643588750073482754583379707570953805820261007616198865","seed":8512550636053661315222643588750073482754583379707570953805820261007616198865,"line":135,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name Type Size Value \n","--------------------------------------\n","exp_item pattgen_item - @11284\n"]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.25742686694851971328350610556024018255537133386745567748792686860339924655165","seed":25742686694851971328350610556024018255537133386745567748792686860339924655165,"line":132,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name Type Size Value \n","--------------------------------------\n","exp_item pattgen_item - @11401\n"]},{"name":"pattgen_stress_all","qual_name":"37.pattgen_stress_all.86884614491216288363782956889135900537198600131222106808935981201949646606028","seed":86884614491216288363782956889135900537198600131222106808935981201949646606028,"line":146,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11278\n"]},{"name":"pattgen_stress_all","qual_name":"41.pattgen_stress_all.33192926081947872392690131187501057334170697074710953293119443777763287464417","seed":33192926081947872392690131187501057334170697074710953293119443777763287464417,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11351\n"]},{"name":"pattgen_stress_all","qual_name":"45.pattgen_stress_all.34907450077330823520125474360677930249761479578274306146223284395370400584243","seed":34907450077330823520125474360677930249761479578274306146223284395370400584243,"line":142,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name Type Size Value \n","------------------------------------\n","exp_item pattgen_item - @11307\n"]}],"Job timed out after * minutes":[{"name":"pattgen_perf","qual_name":"2.pattgen_perf.55170491468947562924873245308313451151126512124484394305852294118874720742056","seed":55170491468947562924873245308313451151126512124484394305852294118874720742056,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"5.pattgen_stress_all.7933576708457097202519765638155600711306182386643421455900672626797003252363","seed":7933576708457097202519765638155600711306182386643421455900672626797003252363,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"6.pattgen_stress_all.85244757369090377800015762501939802472494106170486930032742695025933842691806","seed":85244757369090377800015762501939802472494106170486930032742695025933842691806,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"7.pattgen_perf.25219161715186827187821989566177843855088353461626400121862783241488564829856","seed":25219161715186827187821989566177843855088353461626400121862783241488564829856,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.41763754907909808012657320397814155174624520010911617523194557995747133124151","seed":41763754907909808012657320397814155174624520010911617523194557995747133124151,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"17.pattgen_perf.60217685440250365068030267533171330826431627261748193372255752469229730758371","seed":60217685440250365068030267533171330826431627261748193372255752469229730758371,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"18.pattgen_perf.3666610595134526540229489874997242310137233950988685277859313411173702586471","seed":3666610595134526540229489874997242310137233950988685277859313411173702586471,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"20.pattgen_stress_all.38364845764959519073287812411154229507001244109956901146460348919617496543273","seed":38364845764959519073287812411154229507001244109956901146460348919617496543273,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"22.pattgen_perf.105379301452486293524689172131983388102986617027050142850881522399392904629590","seed":105379301452486293524689172131983388102986617027050142850881522399392904629590,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"23.pattgen_perf.110389484056894737607310109692876331481782604844479138179351239697384327136793","seed":110389484056894737607310109692876331481782604844479138179351239697384327136793,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"25.pattgen_stress_all.78954200752625307740574742268335701734778124644527142123480235467893612692939","seed":78954200752625307740574742268335701734778124644527142123480235467893612692939,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"30.pattgen_perf.58437405337281389248484859894206471505036783608053085651830094695115398526199","seed":58437405337281389248484859894206471505036783608053085651830094695115398526199,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"32.pattgen_stress_all.18730268462052992262841094444339491835706835299608304850892377210147192681731","seed":18730268462052992262841094444339491835706835299608304850892377210147192681731,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"33.pattgen_perf.106228193148268381963778787099578842277819326615579682799793700067179261020693","seed":106228193148268381963778787099578842277819326615579682799793700067179261020693,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"33.pattgen_stress_all.66840932626914986252645416015018995472976134584851291946487736646566621747150","seed":66840932626914986252645416015018995472976134584851291946487736646566621747150,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"35.pattgen_perf.96830238406565288238203136673090610180625822547526984608856664349767843553137","seed":96830238406565288238203136673090610180625822547526984608856664349767843553137,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"37.pattgen_perf.80140896604531804109478917327863401070273983741819508525731970600275347591699","seed":80140896604531804109478917327863401070273983741819508525731970600275347591699,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"38.pattgen_stress_all.97450717938717644664882312152644232940062692163456133399120270667851161407656","seed":97450717938717644664882312152644232940062692163456133399120270667851161407656,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.3075298393751924809286851786683451781313047747893250389089085814984272633312","seed":3075298393751924809286851786683451781313047747893250389089085814984272633312,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"44.pattgen_perf.109452629950743209504807390537367433967905703787657225892301464320408345163789","seed":109452629950743209504807390537367433967905703787657225892301464320408345163789,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"48.pattgen_perf.22188399833698367705988244211513068645871282806101841957674242833633421858985","seed":22188399833698367705988244211513068645871282806101841957674242833633421858985,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"49.pattgen_stress_all.41257752906741146885963998606177679461725021265517504887846735544331683157618","seed":41257752906741146885963998606177679461725021265517504887846735544331683157618,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all/latest/run.log","log_context":[]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"4.pattgen_inactive_level.41085007275690756134300200670831585480955830617212441021621184460777319493928","seed":41085007275690756134300200670831585480955830617212441021621184460777319493928,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10020757611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"13.pattgen_inactive_level.67287080023841843208850764003401288391942991679649517671356312560125407948449","seed":67287080023841843208850764003401288391942991679649517671356312560125407948449,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10023893747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"pattgen_inactive_level","qual_name":"7.pattgen_inactive_level.90066999016733482887071154096551064196835794865259159045857823854419608963830","seed":90066999016733482887071154096551064196835794865259159045857823854419608963830,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10005285625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"8.pattgen_perf.28189171288295266122037077736231804101257271706307089445468165726809778175533","seed":28189171288295266122037077736231804101257271706307089445468165726809778175533,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"11.pattgen_perf.88811300864279512077239248166404229857374490187643098327476851087442258955846","seed":88811300864279512077239248166404229857374490187643098327476851087442258955846,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"31.pattgen_perf.39782848379035515641077714007901391125867538660794324301280455203353683247257","seed":39782848379035515641077714007901391125867538660794324301280455203353683247257,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"36.pattgen_perf.105104566073558854296554996980488090124854351858257202760731773804116192782885","seed":105104566073558854296554996980488090124854351858257202760731773804116192782885,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"42.pattgen_perf.105900089419270944007668344114372526713948311824095761589418402490365802651461","seed":105900089419270944007668344114372526713948311824095761589418402490365802651461,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"45.pattgen_perf.70273854524475989138170002389512544623762697865875387505806543791072574238473","seed":70273854524475989138170002389512544623762697865875387505806543791072574238473,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"47.pattgen_perf.97948190913082681680681884556042218886228211736370625525653799737259408830109","seed":97948190913082681680681884556042218886228211736370625525653799737259408830109,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:454) [pattgen_common_vseq] wait timeout occurred!":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.85070663418650184358080869795207111693332672137873005124432108328956837201751","seed":85070663418650184358080869795207111693332672137873005124432108328956837201751,"line":203,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 15549171144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"pattgen_inactive_level","qual_name":"10.pattgen_inactive_level.96531731531995384212133969331582342610446581313403861676044290864023940339174","seed":96531731531995384212133969331582342610446581313403861676044290864023940339174,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10030842830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"18.pattgen_inactive_level.8721769922144502451967307685904586823567192504841108565898316316554239353188","seed":8721769922144502451967307685904586823567192504841108565898316316554239353188,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10006710367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)":[{"name":"pattgen_inactive_level","qual_name":"11.pattgen_inactive_level.11272490389550290205180999435394815941312538554862291870073784878586771061748","seed":11272490389550290205180999435394815941312538554862291870073784878586771061748,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10021575655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"48.pattgen_inactive_level.30178880318718853767308888130818522476763088536694033158758867655586399280274","seed":30178880318718853767308888130818522476763088536694033158758867655586399280274,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10040735363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"19.pattgen_inactive_level.98893372582653980211294496929600895800446835158992436600459542133428303362088","seed":98893372582653980211294496929600895800446835158992436600459542133428303362088,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10004736088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21)":[{"name":"pattgen_inactive_level","qual_name":"21.pattgen_inactive_level.8882334040270569124030491251862271474334464988598417654672178555981034840025","seed":8882334040270569124030491251862271474334464988598417654672178555981034840025,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10026738972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)":[{"name":"pattgen_inactive_level","qual_name":"23.pattgen_inactive_level.28610304039530715408349754805032318279969163044459898644379077904753848403796","seed":28610304039530715408349754805032318279969163044459898644379077904753848403796,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10026764918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26)":[{"name":"pattgen_inactive_level","qual_name":"27.pattgen_inactive_level.61295586650119382379859047514143082770167341508322930947847321135758403037757","seed":61295586650119382379859047514143082770167341508322930947847321135758403037757,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10191932728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"31.pattgen_inactive_level.114558349675997787355292305518882115268807673528983412000813408467246303330259","seed":114558349675997787355292305518882115268807673528983412000813408467246303330259,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10010240568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"34.pattgen_inactive_level.77080140799544750966285845355962689711258481959374707264983739779756518470698","seed":77080140799544750966285845355962689711258481959374707264983739779756518470698,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10013518191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"49.pattgen_inactive_level.24304323731334922452682579689895965479012209551331251840513477106125530872996","seed":24304323731334922452682579689895965479012209551331251840513477106125530872996,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10033803341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19)":[{"name":"pattgen_inactive_level","qual_name":"33.pattgen_inactive_level.60733119024751175204349368760128412291398147351114481970715650320738713750498","seed":60733119024751175204349368760128412291398147351114481970715650320738713750498,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 11015054992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"40.pattgen_inactive_level.61636514014823038157082367681222387015647729471154180637864263738946785795607","seed":61636514014823038157082367681222387015647729471154180637864263738946785795607,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10230578684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]":[{"name":"pattgen_stress_all","qual_name":"40.pattgen_stress_all.29005636460790370011598834809454053036850008750619800024374160769049486718313","seed":29005636460790370011598834809454053036850008750619800024374160769049486718313,"line":118,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name Type Size Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.53333407270345670910243757578236728678465529174800143233745170510553471700435","seed":53333407270345670910243757578236728678465529174800143233745170510553471700435,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 0 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name Type Size Value \n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)":[{"name":"pattgen_inactive_level","qual_name":"41.pattgen_inactive_level.41771984551360685983726082709858998001328266229908739418262031045333173322049","seed":41771984551360685983726082709858998001328266229908739418262031045333173322049,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10148601670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":333,"total":443,"percent":75.16930022573364}