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[`32edacb`](https://github.com/lowrisc/opentitan/tree/32edacb68e9a736ae5909ca16949f5c4ce181520)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-24T04:19:36Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":497.59,"sim_time":431744.365241,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.09,"sim_time":22.912294000000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":3.16,"sim_time":127.274274,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":32.04,"sim_time":531.914029,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":16.54,"sim_time":3646.047728,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":4.36,"sim_time":134.887402,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":3.16,"sim_time":127.274274,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":16.54,"sim_time":3646.047728,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.84,"sim_time":10.796519,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.48,"sim_time":76.509261,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":39,"total":40,"percent":97.5},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.33,"sim_time":162.83737,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.21,"sim_time":3.5325369999999996,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":0.91,"sim_time":4.380063,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":3.16,"sim_time":117.434695,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":3.16,"sim_time":117.434695,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":17.95,"sim_time":7973.643947,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.44,"sim_time":97.367157,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":37.95,"sim_time":76294.272427,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":37.59,"sim_time":12610.960506,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":44.92,"sim_time":13634.304583000001,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":44.92,"sim_time":13634.304583000001,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":28.44,"sim_time":5977.33735,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":28.44,"sim_time":5977.33735,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":28.44,"sim_time":5977.33735,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":28.44,"sim_time":5977.33735,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":28.44,"sim_time":5977.33735,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":27.04,"sim_time":11894.188523,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":35.68,"sim_time":3497.0809759999997,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":35.68,"sim_time":3497.0809759999997,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":35.68,"sim_time":3497.0809759999997,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":53.63,"sim_time":8128.881482000001,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":13.65,"sim_time":1230.9434979999999,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":35.68,"sim_time":3497.0809759999997,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":348.91,"sim_time":132179.448303,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":12.66,"sim_time":1408.36546,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":12.66,"sim_time":1408.36546,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":497.59,"sim_time":431744.365241,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":683.62,"sim_time":187683.14049000002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":605.22,"sim_time":67832.11784,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.14,"sim_time":34.116906,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.19,"sim_time":19.873554,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":6.52,"sim_time":360.979316,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":6.52,"sim_time":360.979316,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.09,"sim_time":22.912294000000003,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":3.16,"sim_time":127.274274,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":16.54,"sim_time":3646.047728,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.7,"sim_time":376.310316,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.09,"sim_time":22.912294000000003,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":3.16,"sim_time":127.274274,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":16.54,"sim_time":3646.047728,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.7,"sim_time":376.310316,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":341,"total":363,"percent":93.93939393939394},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.68,"sim_time":504.246802,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":24.85,"sim_time":834.7648469999999,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":24.85,"sim_time":834.7648469999999,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":199.67,"sim_time":36767.603329000005,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.9,"branch":98.3,"condition_expression":96.53,"toggle":83.54,"fsm":89.36},"assertion":94.76,"functional":98.76},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.102189237059592603111314871627515457119171696335889328121208943393678084230454","seed":102189237059592603111314871627515457119171696335889328121208943393678084230454,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1062604 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1062604 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.62657034904637312921802158019838599027415845575634099626916727570534186105927","seed":62657034904637312921802158019838599027415845575634099626916727570534186105927,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5574262 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5574262 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.55307122907455563634200720278686896333598634624987958556083518729917085475541","seed":55307122907455563634200720278686896333598634624987958556083518729917085475541,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    945897 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    945897 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.109953340802059202111332615169990542487331944558817601214386352769194949203035","seed":109953340802059202111332615169990542487331944558817601214386352769194949203035,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2338242 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2338242 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[919])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.78121981921405726378761631843683536124464018284201315536953203768057315766766","seed":78121981921405726378761631843683536124464018284201315536953203768057315766766,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5089437 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5089437 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.110467177617425798224069008091370484403928711174336113663555248550791386863695","seed":110467177617425798224069008091370484403928711174336113663555248550791386863695,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3112352 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3112352 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.115032616280077764913416212434816614651291047263275592123661891957927183043798","seed":115032616280077764913416212434816614651291047263275592123661891957927183043798,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    812437 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    812437 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.91638118786755409092242571178058959842055368431355304626389869032731713559412","seed":91638118786755409092242571178058959842055368431355304626389869032731713559412,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1031695 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1031695 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[928])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.35287252637219839264998099242352758244453627619182303310666498251170257519882","seed":35287252637219839264998099242352758244453627619182303310666498251170257519882,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1633087 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1633087 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[948])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.94553467810978668620140459016138880425213217377535439083894317856942882068718","seed":94553467810978668620140459016138880425213217377535439083894317856942882068718,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2212537 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2212537 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[978])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.695397516856840791372264968672674783677144261112912615517635206448046976563","seed":695397516856840791372264968672674783677144261112912615517635206448046976563,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    712615 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    712615 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.23154872791013355880052123259695703834653171462304967962925703272851601619889","seed":23154872791013355880052123259695703834653171462304967962925703272851601619889,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3430367 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3430367 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.20887622609982109110382563873046288154554046941904727138078852709423626997137","seed":20887622609982109110382563873046288154554046941904727138078852709423626997137,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1038585 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1038585 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[981])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.60942016645798507393797694170286135244424770095110919102082613886341906741549","seed":60942016645798507393797694170286135244424770095110919102082613886341906741549,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4714093 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4714093 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.64655709182545817652592249404794535199729183579810162825611563660757869514792","seed":64655709182545817652592249404794535199729183579810162825611563660757869514792,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5894108 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5894108 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.38596652343906244482278608032625755389351313000547707275848800446691661823764","seed":38596652343906244482278608032625755389351313000547707275848800446691661823764,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4683341 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4683341 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.49053921035914317777866685283057224209457711973760700635256114174946519078973","seed":49053921035914317777866685283057224209457711973760700635256114174946519078973,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    810003 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    810003 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.26179648953653790877433270318749184430754024638151044743498906063895976730194","seed":26179648953653790877433270318749184430754024638151044743498906063895976730194,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4387341 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4387341 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.60102643960341948251800453846656685877030201323007147952548711973128332928939","seed":60102643960341948251800453846656685877030201323007147952548711973128332928939,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1864448 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1864448 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[966])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.28382734084168663376966136347361323888163469670258175504189748843922591431139","seed":28382734084168663376966136347361323888163469670258175504189748843922591431139,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3610956 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3610956 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[963])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.107270544328173536692201621686838505804988186672047124191536805157654924903850","seed":107270544328173536692201621686838505804988186672047124191536805157654924903850,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1948063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1f2d23 [111110010110100100011] vs 0x0 [0]) \n","UVM_ERROR @   1988063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4ac01a [10010101100000000011010] vs 0x0 [0]) \n","UVM_ERROR @   2075063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6045f7 [11000000100010111110111] vs 0x0 [0]) \n","UVM_ERROR @   2113063 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6f2c62 [11011110010110001100010] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_and_tpm","qual_name":"6.spi_device_flash_and_tpm.83559264272687112820560115675339546642744406311130179807829424904749707846736","seed":83559264272687112820560115675339546642744406311130179807829424904749707846736,"line":94,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log","log_context":["tl_ul_fuzzy_flash_status_q[i] = 0xc3b6ec\n","tl_ul_fuzzy_flash_status_q[i] = 0xc3b6ec\n","tl_ul_fuzzy_flash_status_q[i] = 0xe4f070\n","tl_ul_fuzzy_flash_status_q[i] = 0xe4f070\n"]}]}},"passed":394,"total":416,"percent":94.71153846153847}