TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Wednesday March 19 2025 17:06:27 UTC

GitHub Revision: cf25bf2795

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 26 32 81.25
AES/MASKED 26 32 81.25
AON_TIMER 20 23 86.96
CSRNG 16 19 84.21
DMA 19 21 90.48
EDN 18 21 85.71
HMAC 24 28 85.71
I2C 44 50 88.00
KEYMGR 24 30 80.00
KEYMGR_DPE 12 14 85.71
KMAC/MASKED 34 40 85.00
KMAC/UNMASKED 34 40 85.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 0 39 0.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 0 39 0.00
MBX 11 14 78.57
OTBN 36 41 87.80
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 16 19 84.21
ROM_CTRL/64KB 16 19 84.21
RV_DM/USE_DMI_INTERFACE 0 53 0.00
RV_TIMER 13 16 81.25
SPI_HOST 24 26 92.31
SPI_DEVICE/1R1W 29 33 87.88
SRAM_CTRL/MAIN 27 31 87.10
SRAM_CTRL/RET 27 31 87.10
UART 24 27 88.89
GPIO 25 28 89.29
ALERT_HANDLER 22 26 84.62
CLKMGR 0 27 0.00
OTP_CTRL 20 30 66.67
PWRMGR 0 29 0.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 16 19 84.21
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 46 254 18.11