TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Friday March 28 2025 17:03:27 UTC

GitHub Revision: ad05932fb8

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
AES/UNMASKED 28 32 87.50
AES/MASKED 28 32 87.50
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
DMA 21 21 100.00
EDN 20 21 95.24
HMAC 28 28 100.00
I2C 46 50 92.00
KEYMGR 27 30 90.00
KEYMGR_DPE 14 14 100.00
KMAC/MASKED 36 40 90.00
KMAC/UNMASKED 36 40 90.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 0 39 0.00
LC_CTRL/VOLATILE_UNLOCK_ENABLED 0 39 0.00
MBX 11 14 78.57
OTBN 37 41 90.24
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_DMI_INTERFACE 0 53 0.00
RV_TIMER 15 16 93.75
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
UART 27 27 100.00
AC_RANGE_CHECK 11 16 68.75
ALERT_HANDLER 25 26 96.15
CLKMGR 0 27 0.00
GPIO 27 28 96.43
OTP_CTRL 21 30 70.00
PWRMGR 0 29 0.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 18 19 94.74
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
XBAR_DBG 18 18 100.00
XBAR_MBX 18 18 100.00
CHIP 56 254 22.05