TOP_DARJEELING_BATCH_SIM Simulation Results (Summary)

Wednesday November 12 2025 16:07:41 UTC

GitHub Revision: efa7857

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 987 1241 79.53 --
AES/UNMASKED 987 1241 79.53 91.92
AES/MASKED 987 1241 79.53 95.41
AON_TIMER 987 1241 79.53 97.01
CSRNG 987 1241 79.53 94.46
DMA 987 1241 79.53 90.04
EDN 987 1241 79.53 85.07
ENTROPY_SRC/RNG_16BITS 987 1241 79.53 79.71
HMAC 987 1241 79.53 90.33
I2C 987 1241 79.53 83.26
KEYMGR 987 1241 79.53 92.90
KEYMGR_DPE 987 1241 79.53 76.03
KMAC/MASKED 987 1241 79.53 92.16
KMAC/UNMASKED 987 1241 79.53 90.35
LC_CTRL/VOLATILE_UNLOCK_DISABLED 987 1241 79.53 88.60
LC_CTRL/VOLATILE_UNLOCK_ENABLED 987 1241 79.53 88.26
MBX 987 1241 79.53 92.78
OTBN 987 1241 79.53 93.17
PRIM_ALERT 987 1241 79.53 93.56
PRIM_ESC 987 1241 79.53 85.66
PRIM_LFSR 987 1241 79.53 98.31
PRIM_PRESENT 987 1241 79.53 93.41
PRIM_PRINCE 987 1241 79.53 100.00
ROM_CTRL/32KB 987 1241 79.53 96.80
ROM_CTRL/64KB 987 1241 79.53 97.89
RV_DM/USE_DMI_INTERFACE 987 1241 79.53 74.63
RV_TIMER 987 1241 79.53 98.59
SPI_HOST 987 1241 79.53 95.63
SPI_DEVICE/1R1W 987 1241 79.53 89.29
SRAM_CTRL/MAIN 987 1241 79.53 95.62
SRAM_CTRL/RET 987 1241 79.53 95.73
UART 987 1241 79.53 89.68
AC_RANGE_CHECK 987 1241 79.53 96.59
ALERT_HANDLER 987 1241 79.53 90.42
CLKMGR 987 1241 79.53 72.37
GPIO 987 1241 79.53 81.53
OTP_CTRL 987 1241 79.53 70.94
RSTMGR_CNSTY_CHK 987 1241 79.53 95.87
RSTMGR 987 1241 79.53 98.07
XBAR_MAIN 987 1241 79.53 97.55
XBAR_PERI 987 1241 79.53 88.81
XBAR_DBG 987 1241 79.53 90.93
XBAR_MBX 987 1241 79.53 87.93
CHIP 987 1241 79.53 68.41