Simulation Results: clkmgr

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.07 %
  • code
  • 69.49 %
  • assert
  • 86.36 %
  • func
  • 72.36 %
  • line
  • 82.14 %
  • branch
  • 87.58 %
  • cond
  • 78.28 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
57.89%
V2S
70.59%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.240s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 0.000us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.620s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.700s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.250s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.700s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.660s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.970s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.850s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.240s 0.000us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.640s 0.000us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.570s 0.000us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.640s 0.000us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.690s 0.000us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.790s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.500s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.500s 0.000us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.800s 0.000us 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.700s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.650s 0.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.800s 0.000us 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
clkmgr_csr_aliasing 0.700s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.650s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.430s 0.000us 1 1 100.00
clkmgr_tl_intg_err 0.820s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.050s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.050s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.050s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.050s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.690s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.820s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.640s 0.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.570s 0.000us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.050s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.910s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.430s 0.000us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.430s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.610s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.890s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 35596409038716350187132844661127220883640879936709911404450262347103863234400 75
UVM_ERROR @ 5462770 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 5462770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 41162692436696130000473246769795486066559620345732304965412396017038178107730 76
UVM_ERROR @ 10182512 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 10182512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 37364921447711061349873990737268808475728031797107355967092152041428192956231 78
UVM_ERROR @ 2390874 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 2390874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 94099832219515364394194614817255493910751647035740937765389924477933085297144 141
UVM_ERROR @ 111493093 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 111493093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 75509684464470069787860943964939587341295457360878125524246605493621509003921 74
UVM_ERROR @ 3026801 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 13 [0xd]) reg name: clkmgr_reg_block.io_meas_ctrl_en
UVM_INFO @ 3026801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 85752549595693478666233501527737868104600277946237660826625154782514460699052 75
UVM_ERROR @ 3066099 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 3066099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 46165460475668926372564580648457356212650859855593654442172296219067469276249 101
UVM_ERROR @ 16721923 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 16721923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 22978825981593732006936052708032172967285040701261581594035047814650276734290 75
UVM_ERROR @ 5615132 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 5615132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 25062319024589338871973470808507927320368601771074952510563198307894909325807 76
UVM_ERROR @ 66363961 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 66363961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 73516355996294715905520986083508432557238664581227044751021779657222661381161 75
UVM_ERROR @ 4103596 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 4103596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 84823817995106496923344135272971131362823875307729908036923898903836482981525 75
UVM_ERROR @ 2117624 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (224756 [0x36df4] vs 60554 [0xec8a]) addr 0xac04e2ec read out mismatch
UVM_INFO @ 2117624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---