Simulation Results: edn/edn0

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.08 %
  • code
  • 81.98 %
  • assert
  • 96.31 %
  • func
  • 79.96 %
  • line
  • 97.88 %
  • branch
  • 92.89 %
  • cond
  • 88.10 %
  • toggle
  • 79.93 %
  • FSM
  • 51.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.980s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.510s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.260s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.090s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 0.000us 1 1 100.00
edn_csr_aliasing 1.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.260s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.260s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.260s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.940s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.900s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.730s 0.000us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 0.000us 1 1 100.00
edn_disable_auto_req_mode 1.230s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.520s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.290s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
edn_csr_rw 0.730s 0.000us 1 1 100.00
edn_csr_aliasing 1.260s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.180s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
edn_csr_rw 0.730s 0.000us 1 1 100.00
edn_csr_aliasing 1.260s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.380s 0.000us 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.900s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.900s 0.000us 1 1 100.00
edn_sec_cm 6.230s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.900s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.380s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.130s 0.000us 1 1 100.00