Simulation Results: i2c

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.52 %
  • code
  • 81.77 %
  • assert
  • 96.19 %
  • func
  • 81.61 %
  • line
  • 96.26 %
  • branch
  • 92.48 %
  • cond
  • 87.22 %
  • toggle
  • 89.45 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
95.92%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 24.220s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.220s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.910s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.840s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.190s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.390s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.710s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.840s 0.000us 1 1 100.00
i2c_csr_aliasing 1.390s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.800s 0.000us 0 1 0.00
host_stress_all 1 1 100.00
i2c_host_stress_all 150.580s 0.000us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 11.400s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.720s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 180.530s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 127.110s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.110s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 5.720s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 6.980s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 45.690s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 21.660s 0.000us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.190s 0.000us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.040s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 21.220s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.790s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 3.990s 0.000us 1 1 100.00
i2c_target_intr_smoke 3.250s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.050s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.120s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 7.830s 0.000us 1 1 100.00
i2c_target_stress_rd 3.990s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 1.610s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.370s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 24.330s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.350s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.870s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.800s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.040s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 11.400s 0.000us 1 1 100.00
i2c_host_perf_precise 2.930s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 21.660s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 5.650s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.020s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.710s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.130s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 5.230s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.490s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.600s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.960s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.230s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.230s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.910s 0.000us 1 1 100.00
i2c_csr_rw 0.840s 0.000us 1 1 100.00
i2c_csr_aliasing 1.390s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.880s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.910s 0.000us 1 1 100.00
i2c_csr_rw 0.840s 0.000us 1 1 100.00
i2c_csr_aliasing 1.390s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.180s 0.000us 1 1 100.00
i2c_sec_cm 0.910s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 2.440s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.400s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 3.010s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 99711978825596199663054437116983099442088915444691478114380360072703205122260 110
UVM_ERROR @ 355829994 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 355829994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 68795804540538216792420754658091853273362677662386452552949341923765503421768 84
UVM_ERROR @ 396978157 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 396978157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 37330159354673649632271720824472620745336612643398028709805526966967081535401 78
UVM_ERROR @ 554233107 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
UVM_INFO @ 554233107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 107794016907622058793805708395291445976236429769146802852817827164328419129226 84
UVM_ERROR @ 109514020 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 109514020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 39151513052325418382110734619174060287518127683839813207693413837297027408420 84
UVM_ERROR @ 710999874 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 710999874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---