Simulation Results: otp_ctrl

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.09 %
  • code
  • 71.12 %
  • assert
  • 93.42 %
  • func
  • 54.73 %
  • line
  • 87.43 %
  • branch
  • 83.53 %
  • cond
  • 85.44 %
  • toggle
  • 64.76 %
  • FSM
  • 34.42 %
Validation stages
V1
100.00%
V2
68.00%
V2S
92.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.890s 0.000us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.980s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.600s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.230s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.570s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.790s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.600s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 5.570s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.260s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.460s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 101.290s 0.000us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.040s 0.000us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 2.340s 0.000us 0 1 0.00
otp_ctrl_check_fail 13.440s 0.000us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.990s 0.000us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 16.460s 0.000us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 9.090s 0.000us 0 1 0.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 2.800s 0.000us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.860s 0.000us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 5.580s 0.000us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 104.510s 0.000us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.380s 0.000us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.730s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.310s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.310s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.980s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.600s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 5.570s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.890s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.980s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.600s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 5.570s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.890s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 11.040s 0.000us 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.040s 0.000us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_macro_errs 5.860s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_macro_errs 5.860s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.200s 0.000us 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.040s 0.000us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 13.440s 0.000us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 22.550s 0.000us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.080s 0.000us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.990s 0.000us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.350s 0.000us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.860s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 50.360s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.730s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 101340323239313556730775996186405292296555470313379997900735373671903640804940 165303
UVM_ERROR @ 2307811086 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 2307811086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 100691532574060842456621176221098926483809793170314934263556247576853775761548 413
UVM_ERROR @ 578536390 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 578536390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 78531652224419324151144228184068260000236221680390597342508586127661781812109 89
UVM_ERROR @ 21985126726 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 21985126726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 71781940282014730550074225008546308668034407673554748861293829538236649658675 90
UVM_ERROR @ 54185369432 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 54185369432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 55088717128898762534709549975046567900900436731888283210044322598489716334962 1404
UVM_ERROR @ 87917294 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 87917294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_parallel_lc_req 1492348744336305296614998059343983720877461113494474216466466445627936712492 8738
UVM_ERROR @ 671014473 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (262 [0x106] vs 260 [0x104]) reg name: status, compare_mask 4
UVM_INFO @ 671014473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_dai_errs 43876969779281143124883601136970367978594532629889164816254330063947075668073 1194
UVM_ERROR @ 765027676 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2758609617 [0xa46d0ad1] vs 3966745565 [0xec6fbbdd]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 765027676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 53439643228653308241556468118556546713314260146204957913087038095774125791683 3256
UVM_ERROR @ 872793025 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 872793025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_parallel_key_req 61463784503889974470524499914219689186691499412645611556432572917182189840821 23945
UVM_ERROR @ 6833261518 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 6833261518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 95265715868529896591313784703220320387035968192187143093871203128667755142932 91
UVM_ERROR @ 39668857 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 39668857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---