Simulation Results: prim_esc

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.11 %
  • code
  • 83.02 %
  • assert
  • 85.19 %
  • line
  • 88.99 %
  • branch
  • 77.78 %
  • cond
  • 80.49 %
  • toggle
  • 100.00 %
  • FSM
  • 67.86 %
Validation stages
V1
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
prim_esc_request_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00
prim_ping_req_interrupted_by_esc_req_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00
prim_esc_tx_integrity_errors_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00
prim_esc_reverse_ping_timeout_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00
prim_esc_receiver_counter_fail_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00
prim_esc_handshake_with_rand_reset_test 1 1 100.00
prim_esc_test 0.550s 0.000us 1 1 100.00