Simulation Results: rstmgr

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.30 %
  • code
  • 99.40 %
  • assert
  • 97.62 %
  • func
  • 94.88 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.98 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.080s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.080s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 1.730s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.980s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.310s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.320s 0.000us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.930s 0.000us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.740s 0.000us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.270s 0.000us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.270s 0.000us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.270s 0.000us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.270s 0.000us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.620s 0.000us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.800s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.420s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.420s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 0.000us 1 1 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.980s 0.000us 1 1 100.00
rstmgr_same_csr_outstanding 0.930s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 0.000us 1 1 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00
rstmgr_csr_aliasing 0.980s 0.000us 1 1 100.00
rstmgr_same_csr_outstanding 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 34.730s 0.000us 1 1 100.00
rstmgr_tl_intg_err 3.720s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 34.730s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 34.730s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.720s 0.000us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 0.000us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.320s 0.000us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.850s 0.000us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 34.730s 0.000us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 0.000us 1 1 100.00