Simulation Results

Simulation Results: rv_dm/use_dmi_interface

10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
79.99 %

code
73.76 %

assert
96.16 %

func
70.04 %

line
90.64 %

branch
75.21 %

cond
76.74 %

toggle
69.95 %

FSM
56.25 %

Validation stages

V1		96.77%
V2		75.00%
V2S		100.00%
V3		0.00%
unmapped		0.00%

30/31 passed

96.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	2.120s	0.000us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	0.900s	0.000us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.450s	0.000us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	53.190s	0.000us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.740s	0.000us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	3.870s	0.000us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	14.220s	0.000us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	47.270s	0.000us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	24.700s	0.000us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.110s	0.000us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	2.490s	0.000us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	0.810s	0.000us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.820s	0.000us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	0.800s	0.000us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	1.140s	0.000us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.910s	0.000us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.330s	0.000us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.110s	0.000us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.770s	0.000us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	0.870s	0.000us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	0.810s	0.000us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.880s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.340s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.840s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	35.370s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	56.200s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.500s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	56.200s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.840s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.680s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.700s	0.000us	1	1	100.00

21/28 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	2.120s	0.000us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.110s	0.000us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.840s	0.000us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	1.000s	0.000us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.100s	0.000us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	91.520s	0.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	556.350s	0.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	111.180s	0.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	279.120s	0.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.810s	0.000us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	1.010s	0.000us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.690s	0.000us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.790s	0.000us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm_rand_reset	106.900s	0.000us	1	1	100.00
	rv_dm_tap_fsm	4.070s	0.000us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.740s	0.000us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	1.000s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.810s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	4.380s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	4.380s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	56.200s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	1.340s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.840s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	3.430s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	56.200s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	1.340s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.840s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	3.430s	0.000us	1	1	100.00

V2S

12/12 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_tl_intg_err	9.840s	0.000us	1	1	100.00
	rv_dm_sec_cm	1.440s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	9.840s	0.000us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	1.010s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.820s	0.000us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	1.010s	0.000us	1	1	100.00
	rv_dm_debug_disabled	0.820s	0.000us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	2.120s	0.000us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	0.890s	0.000us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.760s	0.000us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.760s	0.000us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	0.890s	0.000us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	15.670s	0.000us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	542.790s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	29184276242591064737187587170613163879735317290622999602669363122697808134346	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89610541382104290169252169338526663963531282994960341506488403860185897014429	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	76229535580327712080041675962068195662028459323798306051262227230256221485239	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	2762437029664600770882161955195323061551232188100003760226223485477511999584	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	89229361988468097369699000062812874522583104985204339168852542343679542084850	77	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	96771248460805389218386704348069392138279966212103248142880410798486321494230	77	UVM_ERROR @ 196084047 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 196084047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	106060383963025772896308791546835689766430190167215988486204116161186674250814	77	UVM_ERROR @ 109932294 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 109932294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	14345716633025888325963557653006278893572869504550425180866810537204677193179	77	UVM_ERROR @ 99511073 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3994763133 [0xee1b3f7d] vs 0 [0x0]) UVM_INFO @ 99511073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	97819947681334523744755944198236672068268636547450528596514153513296172452669	78	UVM_ERROR @ 473865418 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (125620568 [0x77cd158] vs 0 [0x0]) UVM_INFO @ 473865418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
	rv_dm_stress_all_with_rand_reset	29205753457781205733663015559342513436039836108417611712398689585972356198549	104	UVM_FATAL @ 1754045111 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done) UVM_INFO @ 1754045111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---