Simulation Results: sram_ctrl/ret

 
10/03/2026 16:01:41 DVSim: v1.12.0 sha: 84d71dd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 95.87 %
  • assert
  • 95.79 %
  • func
  • 95.55 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.17 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.140s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.710s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.400s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.140s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.720s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.020s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 515.620s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 265.020s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 40.040s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 496.110s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.570s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 324.530s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 10.340s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 315.350s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 44.840s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 52.650s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 21.870s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 719.300s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.900s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 654.180s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.930s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.650s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.650s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.710s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.770s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 2.660s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.660s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 719.300s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 719.300s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.880s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 324.530s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 324.530s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 324.530s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.570s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.290s 0.000us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.770s 0.000us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.310s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.140s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.140s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 324.530s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.570s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.140s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.880s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 45.740s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 63558909228818042451262758117921207497208640211526000880777048774490000265844 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2291445 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2291445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---