Simulation Results: chip

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.30 %
  • code
  • 64.80 %
  • assert
  • 76.61 %
  • func
  • 69.50 %
  • line
  • 66.75 %
  • branch
  • 73.73 %
  • cond
  • 63.95 %
  • toggle
  • 62.44 %
  • FSM
  • 57.14 %
Validation stages
V1
33.33%
V2
33.45%
V2S
100.00%
V3
0.00%
unmapped
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_uart_tx_rx 0 1 0.00
chip_sw_uart_tx_rx 453.894s 0.000us 0 1 0.00
chip_sw_uart_rx_overflow 0 1 0.00
chip_sw_uart_tx_rx 453.894s 0.000us 0 1 0.00
chip_sw_uart_rand_baudrate 0 1 0.00
chip_sw_uart_rand_baudrate 374.681s 0.000us 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 297.073s 0.000us 0 1 0.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 309.670s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 309.670s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 309.670s 0.000us 1 1 100.00
chip_sw_example_tests 1 4 25.00
chip_sw_example_rom 29.150s 0.000us 0 1 0.00
chip_sw_example_manufacturer 442.631s 0.000us 0 1 0.00
chip_sw_example_concurrency 194.970s 0.000us 1 1 100.00
chip_sw_uart_smoketest_signed 9.094s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
chip_csr_bit_bash 11.190s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 8.390s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 1 0.00
chip_csr_aliasing 8.390s 0.000us 0 1 0.00
xbar_smoke 1 1 100.00
xbar_smoke 9.860s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_spi_device_flash_mode 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 407.615s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 2723.720s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 254.730s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 0 1 0.00
chip_sw_spi_device_tpm 229.453s 0.000us 0 1 0.00
chip_sw_spi_host_tx_rx 0 1 0.00
chip_sw_spi_host_tx_rx 204.387s 0.000us 0 1 0.00
chip_sw_i2c_host_tx_rx 0 1 0.00
chip_sw_i2c_host_tx_rx 250.049s 0.000us 0 1 0.00
chip_sw_i2c_device_tx_rx 0 1 0.00
chip_sw_i2c_device_tx_rx 233.858s 0.000us 0 1 0.00
chip_pin_mux 0 1 0.00
chip_padctrl_attributes 4.070s 0.000us 0 1 0.00
chip_padctrl_attributes 0 1 0.00
chip_padctrl_attributes 4.070s 0.000us 0 1 0.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 435.524s 0.000us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 430.220s 0.000us 0 1 0.00
chip_sw_data_integrity 0 1 0.00
chip_sw_data_integrity_escalation 457.337s 0.000us 0 1 0.00
chip_sw_instruction_integrity 0 1 0.00
chip_sw_data_integrity_escalation 457.337s 0.000us 0 1 0.00
chip_jtag_csr_rw 0 1 0.00
chip_jtag_csr_rw 105.570s 0.000us 0 1 0.00
chip_jtag_mem_access 0 1 0.00
chip_jtag_mem_access 123.650s 0.000us 0 1 0.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 284.160s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 8.793s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 8.336s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 276.050s 0.000us 0 1 0.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 283.320s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 0 1 0.00
chip_sw_aon_timer_irq 425.520s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bark_irq 0 1 0.00
chip_sw_aon_timer_irq 425.520s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 432.120s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 218.890s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 218.890s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 333.600s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 167.150s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 290.320s 0.000us 1 1 100.00
chip_sw_aes_idle 184.120s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 220.380s 0.000us 1 1 100.00
chip_sw_kmac_idle 187.460s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 0 4 0.00
chip_sw_clkmgr_off_aes_trans 200.830s 0.000us 0 1 0.00
chip_sw_clkmgr_off_hmac_trans 194.510s 0.000us 0 1 0.00
chip_sw_clkmgr_off_kmac_trans 195.080s 0.000us 0 1 0.00
chip_sw_clkmgr_off_otbn_trans 192.930s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 39.980s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.430s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.220s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 37.970s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 10.774s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 171.440s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 1 8 12.50
chip_sw_clkmgr_jitter_reduced_freq 324.910s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 43.480s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en_reduced_freq 41.760s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en_reduced_freq 38.800s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 37.220s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 37.350s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 39.620s 0.000us 0 1 0.00
chip_sw_csrng_edn_concurrency_reduced_freq 36.240s 0.000us 0 1 0.00
chip_sw_clkmgr_deep_sleep_frequency 0 1 0.00
chip_sw_ast_clk_outputs 8.604s 0.000us 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 11.252s 0.000us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 10.839s 0.000us 0 1 0.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 347.550s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_all_reset_reqs 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 218.890s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0 1 0.00
chip_sw_pwrmgr_wdog_reset 10.042s 0.000us 0 1 0.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 347.550s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 20.145s 0.000us 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 32.996s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 31.534s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 16.168s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 28.455s 0.000us 0 1 0.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 284.160s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 394.480s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 299.930s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 0 1 0.00
chip_sw_rstmgr_alert_info 362.330s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 182.190s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 9.017s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 0 1 0.00
chip_sw_alert_handler_escalation 9.890s 0.000us 0 1 0.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 9.882s 0.000us 0 1 0.00
chip_sw_alert_handler_crashdump 0 1 0.00
chip_sw_rstmgr_alert_info 362.330s 0.000us 0 1 0.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 286.990s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 8.382s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 9.203s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 10.305s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 10.001s 0.000us 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10.139s 0.000us 0 1 0.00
chip_sw_lc_ctrl_alert_handler_escalation 0 1 0.00
chip_sw_alert_handler_escalation 9.890s 0.000us 0 1 0.00
chip_sw_lc_ctrl_jtag_access 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 104.355s 0.000us 0 1 0.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_lc_ctrl_key_div 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_prod 339.140s 0.000us 0 1 0.00
chip_sw_lc_ctrl_broadcast 2 10 20.00
chip_prim_tl_access 351.660s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 276.050s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 17.710s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 16.367s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 33.118s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 33.931s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 311.250s 0.000us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 735.600s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 11.118s 0.000us 0 1 0.00
chip_sw_aes_enc 1 2 50.00
chip_sw_aes_enc 200.830s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.430s 0.000us 0 1 0.00
chip_sw_aes_gcm 1 2 50.00
chip_sw_aes_enc 200.830s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.430s 0.000us 0 1 0.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 194.230s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 184.120s 0.000us 1 1 100.00
chip_sw_hmac_enc 1 2 50.00
chip_sw_hmac_enc 216.190s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 220.380s 0.000us 1 1 100.00
chip_sw_kmac_enc 2 3 66.67
chip_sw_kmac_mode_cshake 193.820s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 222.810s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 37.970s 0.000us 0 1 0.00
chip_sw_kmac_app_keymgr 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 311.250s 0.000us 0 1 0.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_kmac_app_rom 0 1 0.00
chip_sw_kmac_app_rom 18.158s 0.000us 0 1 0.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 286.240s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 187.460s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 364.470s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 364.470s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 18.016s 0.000us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 208.250s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 1 1 100.00
chip_sw_csrng_edn_concurrency 1800.230s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 0 2 0.00
chip_sw_keymgr_dpe_key_derivation 311.250s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.220s 0.000us 0 1 0.00
chip_sw_otbn_op 1 2 50.00
chip_sw_otbn_ecdsa_op_irq 2476.240s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 39.980s 0.000us 0 1 0.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 290.320s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 290.320s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 290.320s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 412.830s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 735.600s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 735.600s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 1 2 50.00
chip_sw_sram_ctrl_scrambled_access 355.510s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 10.774s 0.000us 0 1 0.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 11.118s 0.000us 0 1 0.00
chip_sw_sram_lc_escalation 0 2 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_data_integrity_escalation 457.337s 0.000us 0 1 0.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_otp_ctrl_keys 3 4 75.00
chip_sw_otbn_mem_scramble 412.830s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 311.250s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 355.510s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.840s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 3 4 75.00
chip_sw_otbn_mem_scramble 412.830s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 311.250s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 355.510s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.840s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program_error 0 1 0.00
chip_sw_lc_ctrl_program_error 9.494s 0.000us 0 1 0.00
chip_sw_otp_ctrl_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 104.355s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals 1 6 16.67
chip_prim_tl_access 351.660s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 17.710s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 16.367s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 33.118s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 33.931s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 46.789s 0.000us 0 1 0.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 351.660s 0.000us 1 1 100.00
chip_sw_otp_ctrl_nvm_cnt 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 51.441s 0.000us 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0 1 0.00
chip_sw_otp_ctrl_sw_parts 9.772s 0.000us 0 1 0.00
chip_sw_ast_clk_outputs 0 1 0.00
chip_sw_ast_clk_outputs 8.604s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 39.980s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.430s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.220s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 37.970s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 10.774s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 171.440s 0.000us 1 1 100.00
chip_sw_soc_proxy_external_reset_requests 0 1 0.00
chip_sw_soc_proxy_smoketest 168.160s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_irqs 0 1 0.00
chip_sw_soc_proxy_smoketest 168.160s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_wakeup_requests 0 1 0.00
chip_sw_soc_proxy_external_wakeup 181.620s 0.000us 0 1 0.00
chip_sw_soc_proxy_gpios 0 1 0.00
chip_sw_soc_proxy_gpios 187.560s 0.000us 0 1 0.00
chip_sw_nmi_irq 0 1 0.00
chip_sw_rv_core_ibex_nmi_irq 363.380s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 221.720s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 192.650s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 170.840s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 394.480s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 394.480s 0.000us 0 1 0.00
chip_sw_smoketest 14 14 100.00
chip_sw_aes_smoketest 158.640s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 163.820s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 139.640s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 149.200s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 154.900s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 189.300s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 170.570s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 194.930s 0.000us 1 1 100.00
chip_sw_otp_ctrl_smoketest 149.410s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 156.830s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 203.400s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 151.420s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 143.300s 0.000us 1 1 100.00
chip_sw_uart_smoketest 154.120s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 9.476s 0.000us 0 1 0.00
chip_sw_signed 0 1 0.00
chip_sw_uart_smoketest_signed 9.094s 0.000us 0 1 0.00
chip_sw_boot 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 407.615s 0.000us 0 1 0.00
chip_sw_secure_boot 0 1 0.00
base_rom_e2e_smoke 8.964s 0.000us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 218.410s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 164.810s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 155.770s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 207.840s 0.000us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_rv_dm_lc_disabled 276.050s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 25.881s 0.000us 0 1 0.00
chip_sw_lc_walkthrough 0 5 0.00
chip_sw_lc_walkthrough_dev 25.258s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 19.729s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 26.871s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_rma 29.604s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 25.881s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 488.670s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 426.590s 0.000us 1 1 100.00
rom_volatile_raw_unlock 8.383s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 8.333s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 378.350s 0.000us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 390.734s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 94.270s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 94.270s 0.000us 0 1 0.00
tl_d_outstanding_access 0 2 0.00
chip_csr_aliasing 8.390s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.610s 0.000us 0 1 0.00
tl_d_partial_access 0 2 0.00
chip_csr_aliasing 8.390s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.610s 0.000us 0 1 0.00
xbar_base_random_sequence 1 1 100.00
xbar_random 97.500s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 9.150s 0.000us 1 1 100.00
xbar_smoke_large_delays 292.350s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 311.960s 0.000us 1 1 100.00
xbar_random_zero_delays 75.220s 0.000us 1 1 100.00
xbar_random_large_delays 726.030s 0.000us 1 1 100.00
xbar_random_slow_rsp 1294.470s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 66.440s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 11.240s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 47.300s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 11.240s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 140.900s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 2761.380s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 54.490s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 322.230s 0.000us 1 1 100.00
xbar_stress_all_with_error 1155.660s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 1956.440s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 868.570s 0.000us 1 1 100.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 9.295s 0.000us 0 1 0.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 8.962s 0.000us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 10.350s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 8.820s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.272s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 8.870s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 8.194s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 8.225s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 8.101s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 9.156s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 9.231s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9.078s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9.256s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 9.720s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 9.046s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 8.872s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 8.604s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 8.732s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 8.865s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 9.069s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 8.772s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 10.001s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 9.252s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 8.452s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 8.794s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 8.339s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 8.322s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 8.244s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 8.807s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 8.262s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 8.419s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 8.696s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 8.494s 0.000us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 8.191s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 8.268s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 7.964s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 9.164s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 8.237s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 8.416s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 8.314s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 8.060s 0.000us 0 1 0.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 9.127s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 269.350s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 127.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 8.652s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 8.527s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 8.372s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 11.166s 0.000us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 208.620s 0.000us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 53.343s 0.000us 0 1 0.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 200.990s 0.000us 0 1 0.00
chip_sw_coremark 0 1 0.00
chip_sw_coremark 9.651s 0.000us 0 1 0.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 14.355s 0.000us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 8.652s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 8.527s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 8.372s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 8.269s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 7.962s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 8.670s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.510s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 20 40.00
chip_sw_rstmgr_rst_cnsty_escalation 955.080s 0.000us 0 1 0.00
chip_sw_aes_gcm 265.420s 0.000us 1 1 100.00
chip_sw_entropy_src_kat_test 179.180s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 182.630s 0.000us 1 1 100.00
chip_plic_all_irqs_0 392.370s 0.000us 1 1 100.00
chip_plic_all_irqs_10 410.390s 0.000us 1 1 100.00
chip_sw_dma_inline_hashing 189.370s 0.000us 1 1 100.00
chip_sw_dma_abort 193.620s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 8.438s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 8.344s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_otbn 8.672s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_sw 8.189s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_otbn 8.717s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_sw 8.384s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_otbn 8.866s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_sw 8.363s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_otbn 8.123s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_sw 8.204s 0.000us 0 1 0.00
chip_sw_entropy_src_smoketest 196.490s 0.000us 1 1 100.00
chip_sw_mbx_smoketest 281.660s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@31745) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 60854619277633179338448811321073946838531441042255024666714065806852053449537 231
UVM_ERROR @ 117.700000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@31745) { a_addr: 'h2214 a_data: 'h8bdced73 a_mask: 'hb a_size: 'h2 a_param: 'h0 a_source: 'hfc a_opcode: 'h1 a_user: 'h25315 d_param: 'h0 d_source: 'hfc d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.700000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 98526987891444198504183288447171323458569017890366132109247933168536051203270 230
UVM_ERROR @ 504.589000 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40524 read out mismatch
UVM_INFO @ 504.589000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
chip_padctrl_attributes 35745886427597492025878119925892595186461369568100701681944839197252226818820 281
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 117
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
chip_csr_bit_bash 98798386518957800105026946485154815484069580663144768539740561763609441880851 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_aliasing 54830858880214594571879796858143538377162476388694673265489558559637619579025 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_same_csr_outstanding 108231045173243632805590869448237473571255674298903427954973134423897064391639 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode
chip_sw_example_rom 80374795468663444376046721055230675261340060650585766007735512690190813087508 284
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_example_manufacturer 62946891304619661884342543181528323361997380313835320105862478348889275353520 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 7.709s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_data_integrity_escalation 42151393888696952106693666718944108268329285310515786863658178594265047018446 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.688s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_wake 111648896228560936424954799185487001412649821823978338315977182596930435210807 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.010s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_retention 94595333804271375508162601286906818241367719862932215763079070908377704254868 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.777s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx 22778438758305422666446593288083038836757747764267641587245001957371499604887 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.851s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_bootstrap 63156621954010012787281528913240987775562276627307182953997823904712724693746 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.301s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_inject_scramble_seed 106366816467163555900160159272358601883432307018215567372173531002038295117548 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.869s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_exit_test_unlocked_bootstrap 22213399570748668050940302400651443851439688297992188654533626065223947272079 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 78.734s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_rand_baudrate 78095006443120411875204379953678230147047467505312251576932974196767710795701 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.174s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_alt_clk_freq 23242022132862072775989527255303324778427405899570229530831592192823873149694 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 34.892s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_host_tx_rx 36151799486970432033121324495864888411621073601173367966259341893914129866713 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.752s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_device_tx_rx 101217646207760835126651643143056718280203807499070618934031996990152213042060 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.214s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_device_tpm 85083082573870161937527012596039034642456495653736248707348717263996042757639 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.320s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_host_tx_rx 96915207173620101773996097200586969542337849058960215424960215268177053498420 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.607s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_otp_hw_cfg 115753820197039979402629029666886097898725740014926707690462634211575697589477 None
Another command (pid=976807) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=973645) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=974349) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_test_unlocked0 59254239786894411583341190327242233002201564294037809584820669808578016203638 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.167s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_dev 78056101878820142677996474333608857423936352330684202850601945546476868778609 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.279s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_prod 63189984506182553247755863051440057802880049976123082492710129439002774144377 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.252s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_rma 91319186123397179443713543435664862752842508695033173973763829748156254455217 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.721s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_vendor_test_csr_access 42590332807166816407716110530354694629908239517051348988067047035563642890373 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.704s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_nvm_cnt 99649830328354917566508330813396629767135441289982413667619875123267955553938 None
Another command (pid=1013571) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=1052553) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=1045726) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_sw_parts 106025244480934557580613148047405019516967817474330722022250673925458056734252 None
Another command (pid=972319) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=980643) is running. Waiting for it to complete on the server (server_pid=861775)...
Another command (pid=1001606) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_transition 105007004163258286896099212694333117811385278878644184231299651804264445008168 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 14.242s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_dev 69758946385628034848416119674326082994760425868371731168127925070781310787322 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.740s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prod 21748066646486063425936815152918583832931480046318878614943660815125113551862 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.747s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prodend 71622643909628670137687582112022003625687204130121796867914316797158019946586 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.764s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_rma 67817777141964861802003928501237144450508516872067643680177425311603496639467 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.221s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_testunlocks 7819635108675712896994098727293470768487360666956400789587222787204878686746 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.052s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_main_power_glitch_reset 26438543992877889873548264161627117288779530929516740087841689836327070994062 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.174s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_power_glitch_reset 108488618937634586886038113358945538414462326968841687967143275642560538010401 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.790s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 63413528649332128664696774432737289553033398287103345061160417954174289153567 None
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.649s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_random_sleep_power_glitch_reset 60926613256197491897530759343192872830210821066545723559071325713524611494834 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.220s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_disabled 17892118954124607227180380798924022042913558248562213748084998918282971079668 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 17.286s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_wdog_reset 22309607471181341789118058190316788335794942991635319868484951030511877481448 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.355s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_test 91372369079647320447280972744916648869854740924860924682609564404860276677687 None
Another command (pid=1195284) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_escalation 51967220116226097260780328355899228275536904223527076766505700002810226602997 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.303s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_reverse_ping_in_deep_sleep 33283294342870456563034452138109263973561482777828619309039061238589267699844 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.299s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_alerts 109890020571107615795155592964356507918729879958050099934164250879893592738438 None
---- STDERR ----
Another command (pid=1209656) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_pings 2696930224025565015663349196999254693054166022239662419471553535463916075091 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.295s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_clkoff 36377330712016848760297945535185902794241399711843005042485359843815992022118 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.277s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_reset_toggle 88492220406262839475308886796634941222630908616289097430653866816665125395903 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.334s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_entropy 10920214771110442974772066705733665044799549424449247039196790061675508171942 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.288s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_csrng_fuse_en_sw_app_read_test 25455140415166076003062237750927125808266558427965029147948286090649339324310 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 7.225s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_kmac_app_rom 60958401669893426624841988278403155987606450551309512018486842477712888594672 None
---- STDERR ----
Another command (pid=1294059) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_scrambled_access_jitter_en 75013688865332886056678216760604282169550886453393175784954073583838972912780 None
---- STDERR ----
Another command (pid=1305782) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_execution_main 70502288801150833828130616897300405952825752982536297716306669359970138226139 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.344s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_coremark 98052422104538298706320294618776841476456221838368976078294499083446362746219 None
Another command (pid=1309397) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_reset_frequency 28999135448013711865643519413481668608385634118618140547983242592560362676819 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.588s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_sleep_frequency 33452858548186779386578214412979052825974624781945898652804090288526597216185 None
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.976s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_ast_clk_outputs 113903915609042950910000443305312630087579976232197154314231823017318259382780 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.289s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_program_error 58883975355757090501245556946504287364005437033197064409870807827386891730930 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.294s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 17550179895513555617750376962520496410195712624879063856813352972551965726888 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_wakeup 104332171212010368002336401660600576781175759934243628434553181451652279326106 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_escalation_reset 98498937131706959418707673110510286259569376576833814630650400219987224202421 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.785s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_power_virus 29196203437229185511772975178830695658111807821570848212050645055195094597168 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.735s, Critical Path: 0.07s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
base_rom_e2e_smoke 21046183212027998264042354681713111568879298273730625314103100320189420448451 None
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_smoke 34064557786099227979742919548670714534384091938429957753811647763636035135042 None
---- STDERR ----
Another command (pid=1428169) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_exception_c 96332581507484438006450145295923808851449508870615476506628971377675272206531 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_output 109706500154448968433845271019199071803451285911179369887871913669984446461456 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 20124167647404837055019361677377066696014269021526889334899210985385434831337 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 54853832680880901136473636060272592366083172586817697564264694495917901337011 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 45561191067620709450205409287459673575950331038202051809409212891097784384189 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 61622928671041579329146988064753119406736595102963061924551654416403598592531 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 93948742393265746428173483479956858365495676581996898134644449966624704373575 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 10315666967702844176682256426122238409573767435077202347357806668078015168511 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 67100733733626194323593338793865674698638359788933215799722279060150728504714 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 8558195265635981409963341968247377399570286135930303229643431184170150358174 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 11883215595914915815098632412448946855773287618071405943315357599109777975497 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 52986378336828806437804959348791820521277414969937795563347509983957295556028 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 8230195623650632147656764216535731781202617708926905742991585928407863666217 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 30297628922795803994347379953649741830379157758683063240310702221150252288210 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 107763989208245280431561654592549486964041902718808002465976779082650576208088 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 13230089828023130878251587339712648975334104880728297022438609188576888540331 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 114942622138221477726102347306260028089240234599363830174222532745756499352282 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 85014159698551273845176922954279081817845918131875793845895026012562049933975 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_dev 51495147834235095585139834695595055296223772572736133744430325540562805952126 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod 7213650111883628996409767820135910479458384616884390379301662067425315627102 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17823626471045543043013748452063726932655386409938008955897209989520718670526 None
---- STDERR ----
Another command (pid=1441241) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_rma 104417041264138082508174665081004427801929193161033136328504329646013379798012 None
---- STDERR ----
Another command (pid=1440223) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 111364333507286697661202848576427777754910411205892628485837582791047493531722 None
---- STDERR ----
Another command (pid=1439654) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_dev 22218539360672754811956498658136328020021057553573515422885644103420066823507 None
---- STDERR ----
Another command (pid=1441482) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod 42466394591662691126261927286796718585692420355778583220564336946303966711883 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 85547599330691225017032520884696987348152068014194793255649970039290775103054 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_rma 52033723640778027909977959640222892247658515847803668752119736104598594958071 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 1897921524075004971978638056662645601493090701950842599385245472821783608905 None
---- STDERR ----
Another command (pid=1444206) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_dev 43931681630685357565399662415892895139391572125209845296711955794093655418198 None
---- STDERR ----
Another command (pid=1444017) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod 74724551434352985177573358923553958925585386938664673985005581475947002698582 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 112596208631779871949897361124105392175544252240899089957453058696199116044132 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_rma 87471631597285729934555433076226437067154638267593079897247816324779952823016 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 43987951699331925725872048965667308333328500712678166173175733107630246837806 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 112165660241692210416688588171856457737735325102816932973340299639908567778193 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 16971038786531079530275378109049031541141202782448902091101265958766697647170 None
---- STDERR ----
Another command (pid=1446764) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 26146859275613716668628142714518667819481964166640589864203205369919570130550 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 50072627171469876655840520010801052948020604963285776871726054053643846111505 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_test_unlocked0 10448641907321893403437788530337427183935196907579063614198268834547028515927 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_dev 48105931778006384830394216218347722551332853708562758160781990366213022604435 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_rma 57062578276446457484459099440558211996099861589522371952330446477349993208093 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_test_unlocked0 55726535159699133579502789255342228464106729729322813715797887079305999603243 None
---- STDERR ----
Another command (pid=1448480) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_dev 96264604540928423079077130439280971873273848920958631065886500873834588007241 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_rma 55034691657566898767006100068938204239416705672838490935174576253761202876646 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_static_critical 33523988173451011842577429584820849488333069717028197470643489163229060206939 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_meas 21449759760685606568840278009901786534184884510673052936902030611358025270913 None
---- STDERR ----
Another command (pid=1449899) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_no_meas 42119901422470612775564562959142352253802429251052213577559376015592125455936 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_invalid_meas 92672925655390783873342378205453536357418456031181577572737718382184447292877 None
---- STDERR ----
Another command (pid=1450448) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 99879652356199705782496093049548377048655137500188895048158154709583249241724 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 61193539902911217498173151340821566925463697498202285795081965926298871096055 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_otbn 112925416010237050623402295683799513242463791989977154350606513431782124527385 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_sw 43432680476308395053838582283609318334460409571371607434058746539412004157689 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_otbn 74176231289233233964056791404445885410100953419241078892102851921775001949066 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_sw 18994437938786161784870366435470894766100996246637212310866371340527649743101 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_otbn 1416427582064252262208388592184750654213439446040033722973625282096402584634 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_sw 112460213364313356188755178989634409678986554065542647908575206174982335080627 None
---- STDERR ----
Another command (pid=1453044) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_otbn 94142470193001160471582783660193641349192909218440900770954543243079264400432 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_sw 42768520153425949403073192613431008112617281154469856190397279575828954731659 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 17130805690779144497122319632654145650456951992096836356739202801923780776887 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 29752651829788508953588790372975905129643693029060063610588713152854273342422 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 27253660980603681082152187579319583311489985312016098128204053486889617463589 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_smoketest_signed 91288735317170219550062637814150139490885962988855379136955646267111660365444 None
---- STDERR ----
Another command (pid=1455032) is running. Waiting for it to complete on the server (server_pid=861775)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_keymgr_functest 87913243276968188344496746815293144580017261196879229020459539493412055240045 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.287s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
chip_sw_all_escalation_resets 61721914101999025651430207725031210077270771267887438083140799869457108246255 329
UVM_ERROR @ 183.440000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 183.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
chip_sw_rstmgr_rst_cnsty_escalation 66928473022167932580678344818321778616212114770581334172654490963842813448939 348
UVM_ERROR @ 947.514000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 947.514000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 88870803479103192779233366939372167673227855417365245689821442609463992288494 332
UVM_ERROR @ 261.806000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 261.806000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 64852682267314738877405374323060315423439420884171045699189469580209842806666 328
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 179.300000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 179.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
chip_sw_rstmgr_alert_info 40608615594217304050514440073609394285466756266504120603271543823844469442175 342
UVM_ERROR @ 331.993000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 331.993000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rstreqs[*]) && (reset_cause != HwReq))'
chip_sw_rstmgr_cpu_info 98506416639333798284787322357994160297265189952973622215273187956011078829703 346
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.432000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_aes_trans 67299491208536923292103343729346371837292838281229505839642823541040090690273 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.192000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.192000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_hmac_trans 11031392112379906091939992403025114848008191472792775264982821836619525937741 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.240000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_kmac_trans 90359307886709302861945734760802480704144312651459695507212902213912930013429 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.208000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_otbn_trans 13685399283732469947596600441659193190443995802071804001876603059050681388297 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.240000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
chip_sw_soc_proxy_smoketest 14806102451217026707016182388496665762210029814442747384644425578655056199436 321
UVM_ERROR @ 155.968000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 155.968000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *
chip_sw_soc_proxy_external_wakeup 70323921436411131541066141153903560753388236266854475764637619451100809496264 319
UVM_ERROR @ 157.390000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.390000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns *
chip_sw_soc_proxy_gpios 26496824768929085188586200035678208581544856567667546580376066668063794318915 319
UVM_ERROR @ 155.147000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 155.147000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec
chip_sw_aon_timer_irq 48328312424107325693029766251846860666152617871956233264869972308729600159103 320
UVM_ERROR @ 517.141000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3564 usec which is not in the range 325 usec and 374 usec
UVM_INFO @ 517.141000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds
chip_sw_aon_timer_wdog_bite_reset 98025588493812608785779280317053931982191871731054288792742248248063482549777 321
UVM_ERROR @ 182.832000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
chip_sw_otbn_ecdsa_op_irq_jitter_en 4644653644470030594408329583503659270840009568656265970684972152324959272702 312
UVM_FATAL @ 10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en 103848333141382463310873139588125686681639475591059879385286144197386682022071 312
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en 77056993846585207920903910528578775224852289141494550469839212201351019836383 312
UVM_FATAL @ 10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en 113149026210083023001786875668793366194179470532503477728252113747428154903120 312
UVM_FATAL @ 10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en 51610167492626146147391858271165325444859671732490404561553190012689259589200 312
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 112713977073115976682933856782244744889574688402775807902328476629323592856993 312
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en_reduced_freq 48370856369962233622989122633528511103736834297920020795301131889913115013123 312
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en_reduced_freq 108562612472455031607346486586389181288815480027214884016215093234171911129880 312
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 44620181846286220557145815300332714778523036301918297035382575660630578928856 312
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 114155453623520500708221144023927881678254266990858424578111751438676379974055 312
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 49340782784864978024707240732341135335217425070635168654532547591357844626108 312
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_edn_concurrency_reduced_freq 23022178727208254886596910829271706550761527752964947912329821221513748657967 312
UVM_FATAL @ 10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired
chip_sw_rv_core_ibex_nmi_irq 58174081292259030707691810576390990651711828279456658429911285508553291836524 322
UVM_ERROR @ 271.340000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 271.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP
chip_sw_keymgr_dpe_key_derivation 7805681099630271259684401066454111912936159033350927619599643827343098012914 340
UVM_ERROR @ 306.976000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (8573373129077216952009151236136894574026675935348091287072827377776944131617891774816530368784925378521148170622771829618937225423455546796792448144464988 [0xa3b1c661aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd325e776907f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 306.976000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_prod 8512879628043335386529899946434048784653210474599431582538303991537175845546 340
UVM_ERROR @ 307.011000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5036931123605673724375762633164739251249311019831130106072030753676945896343415196726969515396454768483354354816609086384054027859555060808777918606302300 [0x602c01a8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3e67ab1597f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 307.011000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_jtag_csr_rw 97557561641300898754282679456200343874826134953241026213881239092219066867044 5950
UVM_ERROR @ 117.009000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: 'h30480000 a_data: 'hab024e17 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h0 a_user: 'h26925 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 67741281577857119352839985094196584196656874435619122450164789044074894887986 5950
UVM_ERROR @ 117.026000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: 'h30480000 a_data: 'hd09aaef2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h0 a_user: 'h2690a d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
chip_sw_dma_abort 97798479890146981329540995868352394586982522605437399452226723639749300799317 327
UVM_FATAL @ 191.800000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 191.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---