Simulation Results: clkmgr

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.89 %
  • code
  • 86.96 %
  • assert
  • 94.01 %
  • func
  • 73.71 %
  • line
  • 91.48 %
  • branch
  • 93.90 %
  • cond
  • 88.17 %
  • toggle
  • 98.77 %
  • FSM
  • 62.50 %
Validation stages
V1
62.50%
V2
73.68%
V2S
41.18%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.300s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.300s 0.000us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.340s 0.000us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.340s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.510s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
clkmgr_csr_aliasing 1.340s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.800s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.650s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.890s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.300s 0.000us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 0.890s 0.000us 1 1 100.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.670s 0.000us 0 1 0.00
frequency_overflow 1 1 100.00
clkmgr_frequency 0.890s 0.000us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 3.400s 0.000us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.840s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.380s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.380s 0.000us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.300s 0.000us 1 1 100.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
clkmgr_csr_aliasing 1.340s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.380s 0.000us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.300s 0.000us 1 1 100.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
clkmgr_csr_aliasing 1.340s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.380s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_tl_intg_err 0.660s 0.000us 0 1 0.00
clkmgr_sec_cm 1.070s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.410s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.410s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.410s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.410s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.930s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.660s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 0.890s 0.000us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.670s 0.000us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.410s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.920s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.070s 0.000us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.760s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.070s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.650s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.480s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 37305815621937740996321917938528176342024565416782348354521614398166061048657 75
UVM_ERROR @ 11135349 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 11135349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 54709192325592122055484973125003246734803251602679053787037748728427831025325 75
UVM_ERROR @ 3053687 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 3053687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_csr_rw 28561211452657768052364216390079138460508015148961529823920986542855095183020 76
UVM_ERROR @ 6015663 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 6015663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 111438370239258158697332236555361106044075263274737800248107774801178689772988 75
UVM_ERROR @ 50359451 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 50359451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 98882212638666104274990043968447665251008898817422240091335903232481222729206 75
UVM_ERROR @ 56593130 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xe399ee24 read out mismatch
UVM_INFO @ 56593130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 33368883478112381508983446701135353448306635362329026467954692506320995683938 78
UVM_ERROR @ 5579088 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 5579088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 8535985729008484806679513628365247662015459012813221792601533801271571956890 74
UVM_ERROR @ 8103035 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 11 [0xb]) reg name: clkmgr_reg_block.io_meas_ctrl_en
UVM_INFO @ 8103035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 52334226509424321332079543784322601694731911889860816203568971091989448659579 108
UVM_ERROR @ 36405210 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 36405210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_stress_all_with_rand_reset 3228611891459386127596165708285161207549735468006825163055025915104498578910 77
UVM_ERROR @ 82894852 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 82894852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---