Simulation Results: edn/edn0

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.61 %
  • code
  • 80.46 %
  • assert
  • 95.01 %
  • func
  • 81.35 %
  • line
  • 96.85 %
  • branch
  • 89.54 %
  • cond
  • 86.30 %
  • toggle
  • 82.86 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.240s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.330s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 0.000us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 0.000us 1 1 100.00
edn_disable_auto_req_mode 0.890s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.080s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.830s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.830s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.960s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 0.000us 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.960s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.750s 0.000us 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 0.000us 1 1 100.00
edn_sec_cm 18.950s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.750s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 49.180s 0.000us 1 1 100.00