Simulation Results: hmac

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.70 %
  • code
  • 98.02 %
  • assert
  • 96.70 %
  • func
  • 44.39 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.540s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.860s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.550s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.050s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.600s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.860s 0.000us 1 1 100.00
hmac_csr_aliasing 4.050s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 14.900s 0.000us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 14.090s 0.000us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 208.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.800s 0.000us 1 1 100.00
hmac_test_sha512_vectors 312.480s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 9.510s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 0.000us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.100s 0.000us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 783.850s 0.000us 1 1 100.00
error 1 1 100.00
hmac_error 62.720s 0.000us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 5.130s 0.000us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.540s 0.000us 1 1 100.00
hmac_long_msg 14.900s 0.000us 1 1 100.00
hmac_back_pressure 14.090s 0.000us 1 1 100.00
hmac_datapath_stress 783.850s 0.000us 1 1 100.00
hmac_burst_wr 9.100s 0.000us 1 1 100.00
hmac_stress_all 1273.080s 0.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.540s 0.000us 1 1 100.00
hmac_long_msg 14.900s 0.000us 1 1 100.00
hmac_back_pressure 14.090s 0.000us 1 1 100.00
hmac_datapath_stress 783.850s 0.000us 1 1 100.00
hmac_wipe_secret 5.130s 0.000us 1 1 100.00
hmac_test_sha256_vectors 208.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.800s 0.000us 1 1 100.00
hmac_test_sha512_vectors 312.480s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 9.510s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 0.000us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.540s 0.000us 1 1 100.00
hmac_long_msg 14.900s 0.000us 1 1 100.00
hmac_back_pressure 14.090s 0.000us 1 1 100.00
hmac_datapath_stress 783.850s 0.000us 1 1 100.00
hmac_burst_wr 9.100s 0.000us 1 1 100.00
hmac_error 62.720s 0.000us 1 1 100.00
hmac_wipe_secret 5.130s 0.000us 1 1 100.00
hmac_test_sha256_vectors 208.800s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.800s 0.000us 1 1 100.00
hmac_test_sha512_vectors 312.480s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 9.510s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 11.190s 0.000us 1 1 100.00
hmac_stress_all 1273.080s 0.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1273.080s 0.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 0.000us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.580s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.450s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.450s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
hmac_csr_rw 0.860s 0.000us 1 1 100.00
hmac_csr_aliasing 4.050s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.510s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
hmac_csr_rw 0.860s 0.000us 1 1 100.00
hmac_csr_aliasing 4.050s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.830s 0.000us 1 1 100.00
hmac_sec_cm 0.940s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.830s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.540s 0.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.270s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 334.640s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.560s 0.000us 1 1 100.00