Simulation Results: i2c

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.67 %
  • code
  • 81.69 %
  • assert
  • 96.19 %
  • func
  • 82.14 %
  • line
  • 96.45 %
  • branch
  • 92.41 %
  • cond
  • 85.31 %
  • toggle
  • 89.66 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 35.970s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.830s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.750s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.050s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.340s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.040s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.340s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.810s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 190.520s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 40.800s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.730s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 87.670s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 25.010s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.870s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 3.220s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 4.360s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 138.690s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.240s 0.000us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.170s 0.000us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.910s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 328.170s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.770s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 16.840s 0.000us 1 1 100.00
i2c_target_intr_smoke 5.280s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.250s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.130s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 186.750s 0.000us 1 1 100.00
i2c_target_stress_rd 16.840s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 44.480s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.940s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 6.340s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.050s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 10.410s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 3.030s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.240s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 40.800s 0.000us 1 1 100.00
i2c_host_perf_precise 0.840s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.240s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.550s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.160s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.780s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.060s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.030s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.600s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.690s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.640s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.900s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.900s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.750s 0.000us 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.340s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.010s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.750s 0.000us 1 1 100.00
i2c_csr_rw 0.690s 0.000us 1 1 100.00
i2c_csr_aliasing 1.340s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.010s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.040s 0.000us 1 1 100.00
i2c_sec_cm 0.880s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.040s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 19.930s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.770s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 11.130s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 29958669596842456988567310181676407765542319187552930445806525029888007025797 86
UVM_ERROR @ 54736956 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 54736956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 43933250568705687876960693344943264042601765339518485026032976521199931667317 108
UVM_ERROR @ 77941301236 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 77941301236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 41278953343254969482267438343674428921670658917714009900888093163309745399177 84
UVM_ERROR @ 562576819 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 562576819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 90839767785543613362196862381875315226802715012967360593607370118321653223808 78
UVM_ERROR @ 58578359 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 188 [0xbc])
UVM_INFO @ 58578359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 19589679874428445698154435383735186582409809292885294137111010615680794217272 79
UVM_FATAL @ 10543072262 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10543072262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 74387097653796708703372512983469910543179494604969275725149506584440731782193 85
UVM_ERROR @ 664748717 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 664748717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 16376725526839869699311294654617688616712484055102815217175316954514225843778 110
UVM_ERROR @ 886604082 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 886604082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---