Simulation Results: keymgr

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.54 %
  • code
  • 91.84 %
  • assert
  • 97.49 %
  • func
  • 55.30 %
  • line
  • 98.58 %
  • branch
  • 97.13 %
  • cond
  • 93.92 %
  • toggle
  • 88.15 %
  • FSM
  • 81.40 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.870s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 36.860s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.380s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 17.800s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.050s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.730s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.050s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 4.130s 0.000us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.390s 0.000us 1 1 100.00
keymgr_sideload_kmac 2.910s 0.000us 1 1 100.00
keymgr_sideload_aes 1.610s 0.000us 1 1 100.00
keymgr_sideload_otbn 16.840s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.160s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.690s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 4.180s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.050s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 14.520s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.950s 0.000us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 4.960s 0.000us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.750s 0.000us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.850s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.330s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.330s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.380s 0.000us 1 1 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.050s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.730s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.380s 0.000us 1 1 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.050s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.730s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 1.970s 0.000us 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.280s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.280s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.280s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.280s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 5.540s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 1.970s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.280s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 4.130s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_random 36.860s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_random 36.860s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.200s 0.000us 1 1 100.00
keymgr_random 36.860s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.690s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 14.520s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 14.520s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 36.860s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 7.260s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 7.160s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.690s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 7.160s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 7.160s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 7.160s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.070s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 7.160s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.270s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1149) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 53674175328104248685544075562199707488750103861458960642595364716861151879598 140
UVM_ERROR @ 529403965 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 529403965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---