Simulation Results: mbx

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.98 %
  • code
  • 90.14 %
  • assert
  • 96.29 %
  • func
  • 74.51 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 85.57 %
Validation stages
V1
87.50%
V2
81.25%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 24.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 3.000s 0.000us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 53.000s 0.000us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 40.000s 0.000us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 18.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 2.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 0.000us 1 1 100.00
mbx_tl_intg_err 2.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 113154439480503721696877133304962238519275672788633473315686017292858356438635 123
UVM_ERROR @ 145125581 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 145125581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@16610) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
mbx_tl_errors 24975686091920228883977738119427269448664997230058943345099505149081390541992 85
UVM_ERROR @ 2307005 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@16610) { a_addr: 'h70947254 a_data: 'h17a5d827 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hc7 a_opcode: 'h0 a_user: 'h243f3 d_param: 'h0 d_source: 'hc7 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2307005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@15398) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
mbx_csr_mem_rw_with_rand_reset 105922280838024015252810236403165925427249921632608720000156173486437102936113 86
UVM_ERROR @ 3812251 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@15398) { a_addr: 'he70363f4 a_data: 'hed3998f9 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'heb a_opcode: 'h1 a_user: 'h257c7 d_param: 'h0 d_source: 'heb d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3812251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---