Simulation Results: otbn

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.49 %
  • code
  • 93.77 %
  • assert
  • 89.24 %
  • func
  • 97.46 %
  • block
  • 99.05 %
  • line
  • 99.01 %
  • branch
  • 87.60 %
  • toggle
  • 91.03 %
  • FSM
  • 97.44 %
Validation stages
V1
90.91%
V2
73.68%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 0.000us 1 1 100.00
single_binary 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 47.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 14.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 0 1 0.00
otbn_reset 4.000s 0.000us 0 1 0.00
multi_error 1 1 100.00
otbn_multi_err 46.000s 0.000us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 6.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
otbn_stress_all 7.000s 0.000us 0 1 0.00
lc_escalation 0 1 0.00
otbn_escalate 5.000s 0.000us 0 1 0.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 4.000s 0.000us 1 1 100.00
sw_errs_fatal_chk 0 1 0.00
otbn_sw_errs_fatal_chk 4.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 4.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 4.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 4.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 0 2 0.00
otbn_imem_err 5.000s 0.000us 0 1 0.00
otbn_dmem_err 4.000s 0.000us 0 1 0.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 4.000s 0.000us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 0.000us 1 1 100.00
otbn_mac_bignum_acc_err 5.000s 0.000us 1 1 100.00
otbn_urnd_err 4.000s 0.000us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 0.000us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 0.000us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
otbn_tl_intg_err 28.000s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 7.000s 0.000us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 0 1 0.00
otbn_dmem_err 4.000s 0.000us 0 1 0.00
sec_cm_instruction_mem_integrity 0 1 0.00
otbn_imem_err 5.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 28.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_global_esc 0 1 0.00
otbn_escalate 5.000s 0.000us 0 1 0.00
sec_cm_controller_fsm_local_esc 3 5 60.00
otbn_imem_err 5.000s 0.000us 0 1 0.00
otbn_dmem_err 4.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 6.000s 0.000us 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_scramble_ctrl_fsm_local_esc 3 5 60.00
otbn_imem_err 5.000s 0.000us 0 1 0.00
otbn_dmem_err 4.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 6.000s 0.000us 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 0 1 0.00
otbn_escalate 5.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_local_esc 3 5 60.00
otbn_imem_err 5.000s 0.000us 0 1 0.00
otbn_dmem_err 4.000s 0.000us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 6.000s 0.000us 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sca 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
otbn_ctrl_redun 6.000s 0.000us 0 1 0.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 0.000us 1 1 100.00
sec_cm_rnd_bus_consistency 0 1 0.00
otbn_rnd_sec_cm 4.000s 0.000us 0 1 0.00
sec_cm_rnd_rng_digest 0 1 0.00
otbn_rnd_sec_cm 4.000s 0.000us 0 1 0.00
sec_cm_rf_base_data_reg_sw_integrity 0 1 0.00
otbn_rf_base_intg_err 4.000s 0.000us 0 1 0.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 0 1 0.00
otbn_rf_bignum_intg_err 6.000s 0.000us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 3.000s 0.000us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 3.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 0.000us 1 1 100.00
sec_cm_data_mem_sec_wipe 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_instruction_mem_sec_wipe 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_data_reg_sw_sec_wipe 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 6.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_count 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_ctrl_flow_sca 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_data_mem_sw_noaccess 0 1 0.00
otbn_sw_no_acc 5.000s 0.000us 0 1 0.00
sec_cm_key_sideload 0 1 0.00
otbn_single 4.000s 0.000us 0 1 0.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 10.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value.
otbn_single 37154585276461153624689971541711813072429267964637551696924401101040543110796 119
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9270149 PS + 19) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 9270149 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 9270149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 17518334153623708777932307570485902729701061395190483695776379033629546657983 153
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 100687659 PS + 26) Sampled value (27705693502268022) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 100687659 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.subv'
UVM_INFO @ 100687659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_reset 56705847697856241846035485974268168437169569394248597476906884888299322636964 117
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9578059 PS + 25) Sampled value (7092657536580613741) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 9578059 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.subvm'
UVM_INFO @ 9578059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_imem_err 107191879846601141224989824250088411774542091645849912201895508141010790916303 110
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 19445883 PS + 25) Sampled value (27705693535367275) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 19445883 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.unpk'
UVM_INFO @ 19445883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_dmem_err 82841913678133890862083955777338749324012736329610066973536878947516722777711 108
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 4536825 PS + 25) Sampled value (27705693518851633) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 4536825 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn1'
UVM_INFO @ 4536825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 37387978956936592865145923671152699890745035640643757361864770466798540559413 109
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 46407074 PS + 23) Sampled value (7092657458986120813) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 46407074 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.addvm'
UVM_INFO @ 46407074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 19053186611292678179379886708228098572605431043782254645803909238840413646291 111
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 10037146 PS + 28) Sampled value (7092657458986120813) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 10037146 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.addvm'
UVM_INFO @ 10037146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_base_intg_err 102648689394670989384610962524146264388658828047398122490886862449905872612015 112
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 51712185 PS + 23) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 51712185 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 51712185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 28847369397483390848392784683580172904560426000813464141195365493299925121253 144
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 19513556 PS + 23) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 19513556 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 19513556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90578820195950885675478219461738217432364129031585511561795479082570299025999 149
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 222447414 PS + 25) Sampled value (27705693518851633) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4207_1.cur_cp) is an illegal value.
UVM_FATAL @ 222447414 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn1'
UVM_INFO @ 222447414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_errs_fatal_chk 70842576510106385431531922218375271529814711496730222065481347589981825366991 106
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 4413554 PS + 42) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 4413554 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 4413554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rnd_sec_cm 45090830756312914019613546481510818038123750024764110759006657662677470100224 107
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9220007 PS + 41) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 9220007 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 9220007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 85804990268225722328553560325178243254453428326390719727667825351042810945010 108
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 14040299 PS + 30) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4204_1.cur_cp) is an illegal value.
UVM_FATAL @ 14040299 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 14040299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,152): Assertion NoModelErrs has failed
otbn_alu_bignum_mod_err 27026303840131160426670573730988086173550691182811415421144652553996492729372 115
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 14521039 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 14521039 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 14521039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_no_acc 99555926492267290661513843541588160794748514024904234782765053524497576306700 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 14681287 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 14681287 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 14681287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 104079624091167204455666431525548547782595127461861558134258579403261205649254 113
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 4325552 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4325552 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4325552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 35066726525233995884098950758183107880527778117281656143772769471897418308586 96
UVM_FATAL @ 41060660 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 41060660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---