Simulation Results: rv_dm/use_dmi_interface

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.07 %
  • code
  • 73.02 %
  • assert
  • 96.09 %
  • func
  • 71.10 %
  • line
  • 90.16 %
  • branch
  • 74.79 %
  • cond
  • 75.77 %
  • toggle
  • 68.14 %
  • FSM
  • 56.25 %
Validation stages
V1
96.77%
V2
75.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.280s 0.000us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.130s 0.000us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.890s 0.000us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 3.360s 0.000us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 0.820s 0.000us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 1.810s 0.000us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 2.560s 0.000us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 22.450s 0.000us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 37.630s 0.000us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 0.840s 0.000us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.590s 0.000us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.790s 0.000us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.700s 0.000us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.790s 0.000us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 0.750s 0.000us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.830s 0.000us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.110s 0.000us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 0.840s 0.000us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.870s 0.000us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 0.920s 0.000us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.790s 0.000us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.790s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.290s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.590s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 50.500s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 40.440s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 1.440s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 40.440s 0.000us 1 1 100.00
rv_dm_csr_rw 1.590s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.860s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.740s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.280s 0.000us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.960s 0.000us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.850s 0.000us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.790s 0.000us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.190s 0.000us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 577.390s 0.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 154.360s 0.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 331.660s 0.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 140.400s 0.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.690s 0.000us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 3.050s 0.000us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.800s 0.000us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.650s 0.000us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm_rand_reset 7.840s 0.000us 1 1 100.00
rv_dm_tap_fsm 13.620s 0.000us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.710s 0.000us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 6680.990s 0.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.680s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 2.670s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 2.670s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 40.440s 0.000us 1 1 100.00
rv_dm_csr_hw_reset 1.290s 0.000us 1 1 100.00
rv_dm_csr_rw 1.590s 0.000us 1 1 100.00
rv_dm_same_csr_outstanding 4.770s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 40.440s 0.000us 1 1 100.00
rv_dm_csr_hw_reset 1.290s 0.000us 1 1 100.00
rv_dm_csr_rw 1.590s 0.000us 1 1 100.00
rv_dm_same_csr_outstanding 4.770s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 11.330s 0.000us 1 1 100.00
rv_dm_sec_cm 2.770s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 11.330s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 3.050s 0.000us 1 1 100.00
rv_dm_debug_disabled 0.900s 0.000us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 3.050s 0.000us 1 1 100.00
rv_dm_debug_disabled 0.900s 0.000us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.280s 0.000us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.560s 0.000us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.770s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.770s 0.000us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.560s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 5.830s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 222.610s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 68549362746771555661155849348135024367555481589571870290185215396809880883356 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 60549264960518688781567397756286944718618164927360053382642527637115723182464 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 52939657754640156899875092261378050863644324376453489435360387328574720546774 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 47077966141219344332208052108411652654558552507455450357843754949311585208058 86
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 76089073102247262200622606903177474181451381219631270911618665646579603815911 77
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 72350201941819212952739007119609338696841496432478691521233186411198164355037 80
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 54955226750070731805241658189347099880500175233884534307541254985628956835648 77
UVM_ERROR @ 78381623 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 78381623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 64448988543797677099393695978299504149952232833209996018791055350898057227094 84
UVM_ERROR @ 1150857962 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1150857962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 89798154446326872150021794440684592969547920728462204253372442047002037202332 77
UVM_ERROR @ 81951499 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 81951499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 44755311811501263519587808687760882098639907028201520279839465447876665602918 77
UVM_ERROR @ 105070799 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3040465697 [0xb539d321] vs 0 [0x0])
UVM_INFO @ 105070799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---