Simulation Results: spi_host

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.22 %
  • code
  • 94.68 %
  • assert
  • 93.75 %
  • func
  • 88.24 %
  • block
  • 96.42 %
  • line
  • 98.54 %
  • branch
  • 92.15 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 24.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 5.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 5.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 5.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 5.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 4.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 5.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 5.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 6.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 5.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 8.000s 0.000us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 0.000us 1 1 100.00
spi_host_error_cmd 7.000s 0.000us 1 1 100.00
spi_host_event 46.000s 0.000us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 8.000s 0.000us 1 1 100.00
speed 1 1 100.00
spi_host_speed 8.000s 0.000us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 8.000s 0.000us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 90.000s 0.000us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 7.000s 0.000us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 8.000s 0.000us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 8.000s 0.000us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 24.000s 0.000us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 24.000s 0.000us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 398.000s 0.000us 0 1 0.00
spien 1 1 100.00
spi_host_spien 9.000s 0.000us 1 1 100.00
stall 0 1 0.00
spi_host_status_stall 410.000s 0.000us 0 1 0.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 16.000s 0.000us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 6.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 6.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 6.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 6.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 5.000s 0.000us 1 1 100.00
spi_host_csr_rw 5.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 5.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 5.000s 0.000us 1 1 100.00
spi_host_csr_rw 5.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 5.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 6.000s 0.000us 1 1 100.00
spi_host_tl_intg_err 6.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 6.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 56.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 40751204873565425974063667891578133689249953802351809482624485613771886518946 7562
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 83124957393306794347644230559877417739568397690846052194285709699285863278849 300
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---