Simulation Results: uart

 
11/03/2026 16:03:29 DVSim: v1.14.0 sha: bb630fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.12 %
  • code
  • 95.81 %
  • assert
  • 97.12 %
  • func
  • 56.43 %
  • line
  • 99.17 %
  • branch
  • 96.50 %
  • cond
  • 96.03 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.680s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.850s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.720s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 81.920s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.680s 0.000us 1 1 100.00
uart_tx_rx 81.920s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.660s 0.000us 1 1 100.00
uart_rx_parity_err 17.680s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 81.920s 0.000us 1 1 100.00
uart_intr 10.660s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 23.460s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 18.960s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 77.550s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.660s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.660s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.660s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 290.190s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.840s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.840s 0.000us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.080s 0.000us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.750s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.820s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 20.500s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 326.950s 0.000us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 15.800s 0.000us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.540s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.550s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.100s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.100s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 0.000us 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.720s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.720s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 0.000us 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.720s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.720s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.690s 0.000us 1 1 100.00
uart_tl_intg_err 1.110s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 8.410s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 62389010888873147193843069732725157906589271552778701321564481025209436874823 76
UVM_ERROR @ 4851092942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4851092942 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 5182892942 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_INFO @ 5183132942 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/7
UVM_ERROR @ 5192772942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_stress_all 55598298414298206002030554754276527011836560658143035261447074786589421392760 80
UVM_ERROR @ 14693554685 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 14711346921 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10, clk_pulses: 0
UVM_ERROR @ 14711367755 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (17 [0x11] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 14778505320 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12, clk_pulses: 0
UVM_ERROR @ 14778515737 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty