Simulation Results: alert_handler

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.74 %
  • code
  • 91.16 %
  • assert
  • 89.92 %
  • func
  • 76.15 %
  • line
  • 99.67 %
  • branch
  • 99.76 %
  • cond
  • 93.78 %
  • toggle
  • 93.23 %
  • FSM
  • 69.35 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.200s 0.000us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.740s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 176.660s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 98.440s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.200s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.740s 0.000us 1 1 100.00
alert_handler_csr_aliasing 98.440s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 34.300s 0.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 17.000s 0.000us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 829.880s 0.000us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 14.360s 0.000us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 48.440s 0.000us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 30.860s 0.000us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 141.770s 0.000us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 689.270s 0.000us 1 1 100.00
alert_handler_lpg_stub_clk 1415.820s 0.000us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 101.520s 0.000us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 11.550s 0.000us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.680s 0.000us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.340s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.390s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.390s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.200s 0.000us 1 1 100.00
alert_handler_csr_rw 3.740s 0.000us 1 1 100.00
alert_handler_csr_aliasing 98.440s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 15.910s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.200s 0.000us 1 1 100.00
alert_handler_csr_rw 3.740s 0.000us 1 1 100.00
alert_handler_csr_aliasing 98.440s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 15.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 266.060s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 266.060s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 266.060s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 266.060s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 476.300s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
alert_handler_tl_intg_err 2.650s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.650s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 266.060s 0.000us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 10.980s 0.000us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 14.360s 0.000us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 689.270s 0.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 14.360s 0.000us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 829.880s 0.000us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 829.880s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 26.100s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 98.780s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 82208526178993687659624334599077910127762056141068576199125771462072990602704 109
UVM_ERROR @ 5587251687 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 5587251687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 35397980841061772402338094640407632867727337748289144875656541273854718179238 144
UVM_ERROR @ 4386216685 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4386216685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---