Simulation Results: chip

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.67 %
  • code
  • 64.07 %
  • assert
  • 76.61 %
  • func
  • 56.33 %
  • line
  • 66.69 %
  • branch
  • 72.50 %
  • cond
  • 61.49 %
  • toggle
  • 62.53 %
  • FSM
  • 57.14 %
Validation stages
V1
33.33%
V2
33.45%
V2S
100.00%
V3
0.00%
unmapped
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_uart_tx_rx 0 1 0.00
chip_sw_uart_tx_rx 110.466s 0.000us 0 1 0.00
chip_sw_uart_rx_overflow 0 1 0.00
chip_sw_uart_tx_rx 110.466s 0.000us 0 1 0.00
chip_sw_uart_rand_baudrate 0 1 0.00
chip_sw_uart_rand_baudrate 88.803s 0.000us 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 76.990s 0.000us 0 1 0.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 330.260s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 330.260s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 330.260s 0.000us 1 1 100.00
chip_sw_example_tests 1 4 25.00
chip_sw_example_rom 30.600s 0.000us 0 1 0.00
chip_sw_example_manufacturer 144.490s 0.000us 0 1 0.00
chip_sw_example_concurrency 190.240s 0.000us 1 1 100.00
chip_sw_uart_smoketest_signed 9.319s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
chip_csr_bit_bash 9.130s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 8.140s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 1 0.00
chip_csr_aliasing 8.140s 0.000us 0 1 0.00
xbar_smoke 1 1 100.00
xbar_smoke 9.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_spi_device_flash_mode 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 91.027s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 2482.950s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 294.820s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 0 1 0.00
chip_sw_spi_device_tpm 74.438s 0.000us 0 1 0.00
chip_sw_spi_host_tx_rx 0 1 0.00
chip_sw_spi_host_tx_rx 73.127s 0.000us 0 1 0.00
chip_sw_i2c_host_tx_rx 0 1 0.00
chip_sw_i2c_host_tx_rx 71.372s 0.000us 0 1 0.00
chip_sw_i2c_device_tx_rx 0 1 0.00
chip_sw_i2c_device_tx_rx 59.575s 0.000us 0 1 0.00
chip_pin_mux 0 1 0.00
chip_padctrl_attributes 3.410s 0.000us 0 1 0.00
chip_padctrl_attributes 0 1 0.00
chip_padctrl_attributes 3.410s 0.000us 0 1 0.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 124.558s 0.000us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 119.346s 0.000us 0 1 0.00
chip_sw_data_integrity 0 1 0.00
chip_sw_data_integrity_escalation 116.982s 0.000us 0 1 0.00
chip_sw_instruction_integrity 0 1 0.00
chip_sw_data_integrity_escalation 116.982s 0.000us 0 1 0.00
chip_jtag_csr_rw 0 1 0.00
chip_jtag_csr_rw 97.350s 0.000us 0 1 0.00
chip_jtag_mem_access 0 1 0.00
chip_jtag_mem_access 119.830s 0.000us 0 1 0.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 273.730s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 11.606s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 9.761s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 152.990s 0.000us 0 1 0.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 259.140s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 0 1 0.00
chip_sw_aon_timer_irq 440.790s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bark_irq 0 1 0.00
chip_sw_aon_timer_irq 440.790s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 409.570s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 223.390s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 223.390s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 359.860s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 168.110s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 310.750s 0.000us 1 1 100.00
chip_sw_aes_idle 209.680s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 216.800s 0.000us 1 1 100.00
chip_sw_kmac_idle 190.190s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 0 4 0.00
chip_sw_clkmgr_off_aes_trans 201.210s 0.000us 0 1 0.00
chip_sw_clkmgr_off_hmac_trans 186.100s 0.000us 0 1 0.00
chip_sw_clkmgr_off_kmac_trans 197.260s 0.000us 0 1 0.00
chip_sw_clkmgr_off_otbn_trans 173.180s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 41.300s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.540s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 42.900s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.440s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.245s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 162.620s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 1 8 12.50
chip_sw_clkmgr_jitter_reduced_freq 325.640s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 43.740s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en_reduced_freq 40.770s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en_reduced_freq 39.080s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 36.940s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 38.650s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 39.220s 0.000us 0 1 0.00
chip_sw_csrng_edn_concurrency_reduced_freq 41.950s 0.000us 0 1 0.00
chip_sw_clkmgr_deep_sleep_frequency 0 1 0.00
chip_sw_ast_clk_outputs 9.717s 0.000us 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 16.237s 0.000us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 17.940s 0.000us 0 1 0.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 389.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_all_reset_reqs 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 223.390s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0 1 0.00
chip_sw_pwrmgr_wdog_reset 13.818s 0.000us 0 1 0.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 389.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 38.693s 0.000us 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 9.198s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 13.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 29.986s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 9.505s 0.000us 0 1 0.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 273.730s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 386.950s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 320.140s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 0 1 0.00
chip_sw_rstmgr_alert_info 376.610s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 197.830s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 9.814s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 0 1 0.00
chip_sw_alert_handler_escalation 9.145s 0.000us 0 1 0.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 9.673s 0.000us 0 1 0.00
chip_sw_alert_handler_crashdump 0 1 0.00
chip_sw_rstmgr_alert_info 376.610s 0.000us 0 1 0.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 439.310s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 8.702s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 9.396s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 10.178s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 10.032s 0.000us 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11.034s 0.000us 0 1 0.00
chip_sw_lc_ctrl_alert_handler_escalation 0 1 0.00
chip_sw_alert_handler_escalation 9.145s 0.000us 0 1 0.00
chip_sw_lc_ctrl_jtag_access 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 34.069s 0.000us 0 1 0.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_lc_ctrl_key_div 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_prod 301.200s 0.000us 0 1 0.00
chip_sw_lc_ctrl_broadcast 2 10 20.00
chip_prim_tl_access 502.740s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 152.990s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 39.474s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 24.662s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 31.998s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 23.552s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 337.790s 0.000us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 728.180s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 8.549s 0.000us 0 1 0.00
chip_sw_aes_enc 1 2 50.00
chip_sw_aes_enc 233.430s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.540s 0.000us 0 1 0.00
chip_sw_aes_gcm 1 2 50.00
chip_sw_aes_enc 233.430s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.540s 0.000us 0 1 0.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 168.850s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 209.680s 0.000us 1 1 100.00
chip_sw_hmac_enc 1 2 50.00
chip_sw_hmac_enc 196.600s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 42.900s 0.000us 0 1 0.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 216.800s 0.000us 1 1 100.00
chip_sw_kmac_enc 2 3 66.67
chip_sw_kmac_mode_cshake 178.470s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 224.130s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_kmac_app_keymgr 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 337.790s 0.000us 0 1 0.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_kmac_app_rom 0 1 0.00
chip_sw_kmac_app_rom 13.810s 0.000us 0 1 0.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 287.070s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 190.190s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 399.730s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 399.730s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 16.019s 0.000us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 201.530s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 1 1 100.00
chip_sw_csrng_edn_concurrency 1138.940s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 0 2 0.00
chip_sw_keymgr_dpe_key_derivation 337.790s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.440s 0.000us 0 1 0.00
chip_sw_otbn_op 1 2 50.00
chip_sw_otbn_ecdsa_op_irq 2434.800s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 41.300s 0.000us 0 1 0.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 310.750s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 310.750s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 310.750s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 421.700s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 728.180s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 728.180s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 1 2 50.00
chip_sw_sram_ctrl_scrambled_access 357.490s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.245s 0.000us 0 1 0.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 8.549s 0.000us 0 1 0.00
chip_sw_sram_lc_escalation 0 2 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_data_integrity_escalation 116.982s 0.000us 0 1 0.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_otp_ctrl_keys 3 4 75.00
chip_sw_otbn_mem_scramble 421.700s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 337.790s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 357.490s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 190.570s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 3 4 75.00
chip_sw_otbn_mem_scramble 421.700s 0.000us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 337.790s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 357.490s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 190.570s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program_error 0 1 0.00
chip_sw_lc_ctrl_program_error 8.952s 0.000us 0 1 0.00
chip_sw_otp_ctrl_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 34.069s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals 1 6 16.67
chip_prim_tl_access 502.740s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 39.474s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 24.662s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 31.998s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 23.552s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 19.078s 0.000us 0 1 0.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 502.740s 0.000us 1 1 100.00
chip_sw_otp_ctrl_nvm_cnt 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 17.826s 0.000us 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0 1 0.00
chip_sw_otp_ctrl_sw_parts 18.161s 0.000us 0 1 0.00
chip_sw_ast_clk_outputs 0 1 0.00
chip_sw_ast_clk_outputs 9.717s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 41.300s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.540s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 42.900s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 42.440s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 35.990s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.245s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 162.620s 0.000us 1 1 100.00
chip_sw_soc_proxy_external_reset_requests 0 1 0.00
chip_sw_soc_proxy_smoketest 190.720s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_irqs 0 1 0.00
chip_sw_soc_proxy_smoketest 190.720s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_wakeup_requests 0 1 0.00
chip_sw_soc_proxy_external_wakeup 180.200s 0.000us 0 1 0.00
chip_sw_soc_proxy_gpios 0 1 0.00
chip_sw_soc_proxy_gpios 184.650s 0.000us 0 1 0.00
chip_sw_nmi_irq 0 1 0.00
chip_sw_rv_core_ibex_nmi_irq 372.600s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 216.730s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 202.650s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 190.570s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 386.950s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 386.950s 0.000us 0 1 0.00
chip_sw_smoketest 14 14 100.00
chip_sw_aes_smoketest 168.520s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 174.090s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 143.490s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 141.930s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 176.800s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 186.130s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 186.270s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 199.810s 0.000us 1 1 100.00
chip_sw_otp_ctrl_smoketest 152.170s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 143.580s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 208.880s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 140.150s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 153.570s 0.000us 1 1 100.00
chip_sw_uart_smoketest 160.010s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 9.881s 0.000us 0 1 0.00
chip_sw_signed 0 1 0.00
chip_sw_uart_smoketest_signed 9.319s 0.000us 0 1 0.00
chip_sw_boot 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 91.027s 0.000us 0 1 0.00
chip_sw_secure_boot 0 1 0.00
base_rom_e2e_smoke 8.656s 0.000us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 182.570s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 171.880s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 167.330s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 214.360s 0.000us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_rv_dm_lc_disabled 152.990s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 44.340s 0.000us 0 1 0.00
chip_sw_lc_walkthrough 0 5 0.00
chip_sw_lc_walkthrough_dev 16.182s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 14.207s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 42.589s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_rma 44.812s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 44.340s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 631.800s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 488.150s 0.000us 1 1 100.00
rom_volatile_raw_unlock 8.346s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 8.684s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 81.433s 0.000us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 81.913s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 99.780s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 99.780s 0.000us 0 1 0.00
tl_d_outstanding_access 0 2 0.00
chip_csr_aliasing 8.140s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.540s 0.000us 0 1 0.00
tl_d_partial_access 0 2 0.00
chip_csr_aliasing 8.140s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.540s 0.000us 0 1 0.00
xbar_base_random_sequence 1 1 100.00
xbar_random 66.750s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 8.740s 0.000us 1 1 100.00
xbar_smoke_large_delays 297.500s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 366.840s 0.000us 1 1 100.00
xbar_random_zero_delays 16.900s 0.000us 1 1 100.00
xbar_random_large_delays 943.310s 0.000us 1 1 100.00
xbar_random_slow_rsp 234.750s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 70.390s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 104.900s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 215.090s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 104.900s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 38.520s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 1208.170s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 86.580s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 734.920s 0.000us 1 1 100.00
xbar_stress_all_with_error 399.400s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 311.050s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 530.820s 0.000us 1 1 100.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 10.095s 0.000us 0 1 0.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 9.704s 0.000us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 9.191s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 9.098s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.533s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 8.699s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.850s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 9.035s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 8.712s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 9.294s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 9.917s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9.107s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 8.343s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 9.280s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 8.895s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9.043s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 8.850s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 10.042s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 9.534s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 10.728s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 9.474s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 9.862s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 10.358s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 8.799s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 9.465s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 9.149s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 9.915s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 8.778s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 8.773s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 9.181s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 8.649s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 9.568s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 9.608s 0.000us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 9.182s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 9.303s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 8.515s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 8.597s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 9.163s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 8.544s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 8.596s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 9.042s 0.000us 0 1 0.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 9.841s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 223.560s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 132.230s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 9.162s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 8.882s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 9.340s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 14.224s 0.000us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 932.080s 0.000us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 14.476s 0.000us 0 1 0.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 210.900s 0.000us 0 1 0.00
chip_sw_coremark 0 1 0.00
chip_sw_coremark 8.456s 0.000us 0 1 0.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 9.650s 0.000us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 9.162s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 8.882s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 9.340s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 9.618s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 8.678s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 8.754s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 9.192s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 20 40.00
chip_sw_rstmgr_rst_cnsty_escalation 955.670s 0.000us 0 1 0.00
chip_sw_aes_gcm 239.660s 0.000us 1 1 100.00
chip_sw_entropy_src_kat_test 192.980s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 166.820s 0.000us 1 1 100.00
chip_plic_all_irqs_0 436.310s 0.000us 1 1 100.00
chip_plic_all_irqs_10 360.950s 0.000us 1 1 100.00
chip_sw_dma_inline_hashing 211.940s 0.000us 1 1 100.00
chip_sw_dma_abort 230.800s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 9.092s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 8.380s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_otbn 9.117s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_sw 8.620s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_otbn 8.652s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_sw 8.728s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_otbn 8.939s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_sw 9.041s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_otbn 8.506s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_sw 8.741s 0.000us 0 1 0.00
chip_sw_entropy_src_smoketest 186.870s 0.000us 1 1 100.00
chip_sw_mbx_smoketest 301.860s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)'
chip_tl_errors 61277443234782254732387990273131428598121863412066655482144245334294443759042 232
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 117.996000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 117.996000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 61082053305472654683673033932027339594013172925111777722713060243343328653848 213
UVM_ERROR @ 250.936000 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40448 read out mismatch
UVM_INFO @ 250.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
chip_padctrl_attributes 23523368141212750816679446963495876152744539625649276194467705025086334899701 281
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 117
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
chip_csr_bit_bash 5088423324044544446352134279243802157515732199557096608173312687132301656894 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_aliasing 72038368857323480601236502932863834235027282239218437713761277298025944462249 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_same_csr_outstanding 431320643193380125329503616079174888540687810143679990460154993112899530160 136
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode
chip_sw_example_rom 7052313640251808234742007440141587815315366910257555068211405221679241130317 284
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_example_manufacturer 71452842404462284140184651952625208174090169913758027734263532627958874503089 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.600s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_data_integrity_escalation 58788651526361254973473238473000330290318455256276405361177797089837700090081 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.778s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_wake 60257021910990321096058053836132615668946538690730287399785586400253916318433 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.038s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_retention 67925882003624559039423294486004314888695643581329482161892764223646646600650 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.613s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx 76910340455597882973989603825753155747712321487173612457104181062789380483879 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.729s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_bootstrap 60434720223453682653606363962590479497091060410441673413821219003436693210291 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.662s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_inject_scramble_seed 45666356419484306874379181665174739363927521375031041732081257408132385237780 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.147s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_exit_test_unlocked_bootstrap 81015898698190551042783814230888286246006188853930583170158906794003359540558 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.573s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_rand_baudrate 59458707496369611691481720628937479140418835100858316378226018628442092515370 None
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.219s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_alt_clk_freq 92910279649784530962247961123598972269063867551615862676292344094343746556695 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.260s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_host_tx_rx 88880796622034187429934271023419913946943528563278312964606879949944763475325 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 11.061s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_device_tx_rx 54846978612516096906985425634890090885137888790871066444182468030500852549870 None
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.795s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_device_tpm 49971313297275202894050945964849679994813373533032168520146008502845006699781 None
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.851s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_host_tx_rx 36753912143814282422006916926911763141851682687904816555284201093169045480290 None
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 11.582s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_otp_hw_cfg 81526972572024207018380341051529503745411498985757502291726478971686047896699 None
Another command (pid=1018029) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=993606) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=1024305) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_test_unlocked0 20272903791160605965065598139230704169170357389461839805442456196953855453513 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.580s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_dev 13168635763780957017690646790463612255532240485123854706687598264305173112741 None
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.072s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_prod 69475618088740819439013512567501202674120631264786338185816470068611467728744 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.680s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_rma 5596534265958172056509968831007282930921398987394805611219496387991007091400 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.247s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_vendor_test_csr_access 25457448648306909656760144478230690672441209218383773089493045533585389142622 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.200s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_nvm_cnt 52510715292646174244818448799620128501808508197911695179810987489293274905236 None
Another command (pid=1009562) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=1008009) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=1010120) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_sw_parts 19075970317439043084127279691277182627591661569368836030522594170382429689091 None
Another command (pid=1018580) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=993606) is running. Waiting for it to complete on the server (server_pid=903692)...
Another command (pid=1021784) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_transition 74161611547033415001666882383118193122992427921057204152042553869804867337115 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.670s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_dev 56946191838165417581391730554224657477494869886332386165676104269056004562149 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.675s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prod 49496705381392923699788092601635094092033953396232992968054282335752983751659 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.747s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prodend 105755291485913621067798319801282255051897260685760130692216333166423988084795 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.257s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_rma 115732456544893532051312587861787720770504153341434424363953834216376940228917 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.674s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_testunlocks 83850312106067650321366713950582549091513045962515589265842042884660518558394 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.232s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_main_power_glitch_reset 108968120453256250860189694735497118698197046825343432534094597640572082636866 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 5.616s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_power_glitch_reset 85077174111738703298451542760262089116124426385435393094480764721657286687810 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.632s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 33139352278469872271343273407232323408763027210647150751908297351563611777148 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.939s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_random_sleep_power_glitch_reset 38911002550256221738597198895239691477218517633490434970937049323681912619656 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.259s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_disabled 88892213038749399153999416353113381169392421143220810853869821797562690311831 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.453s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_wdog_reset 13073636515494220269414641199191989144412576677606455574275867384087270316263 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.348s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_test 20868106064166636858176580672937088199126010769508003385226652126967162403658 None
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_escalation 103068519901412611528513108108629564021063967320317592327422729411278094221946 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.279s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10023118523720366283859460296593890710883316878182712845369046735879863784458 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.775s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_alerts 16707747409763164153682703444969791897470080315905532621274785164022647108614 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_pings 51160604023152039135595616642062710410233712643001431131249908810943197042623 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.296s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_clkoff 82360052448766088157833342752411667079620492206224761538002197778551602389432 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.246s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_reset_toggle 57210237707315402733539350355160732958771306370403326723129000667961297763898 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.262s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_entropy 33942808120849309611987527759874473243376886670782381986075012151989093358344 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.328s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_csrng_fuse_en_sw_app_read_test 82665471511497255759435795605405578436500144737869951146885473053859014923575 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.290s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_kmac_app_rom 103632969898118865623662706243347077116029615024968769454836472853696569797503 None
---- STDOUT ----
---- STDERR ----
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_scrambled_access_jitter_en 8475919521174456999139382355238917691952570059424507267405205382841859803734 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_execution_main 105858398343815407814209842178912962031697262906506746442672444054204984748422 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.288s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_coremark 94033106663386710497647581584043473988416588178158568178057936736599937125373 None
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_reset_frequency 5466034829732733959256681920682385909193556870535479948855160626288034380623 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.481s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_sleep_frequency 55688997527867240905207731829277864991405139397444361837276451051786394512109 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.532s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_ast_clk_outputs 56128318163087804479809832422654104218516618453967391528569289149801870644060 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.260s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_program_error 89605092272987411044784586249122790425756109991039089787081700095476705937870 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.245s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 7254279948374176736482025319126822704319289249992762532257769664579767588555 None
---- STDERR ----
Another command (pid=1346264) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_wakeup 51796175396386420968106109456243861608285546520870651567294405802350839980174 None
---- STDERR ----
Another command (pid=1346264) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_escalation_reset 22817474575885937236599489221172980715977557396463429722857402250781267953820 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.845s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_power_virus 108910630262857194915506700106126622263151732262829664117872539268741278510140 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.373s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
base_rom_e2e_smoke 50793723760740901203840859594046615984669527700843213726229798638772788178185 None
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_smoke 18632863292755678296983848011483247481286356322000259418590381628253475791482 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_exception_c 9793156202486807137785132344565138249175914702192156303758439987782828653693 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_output 72224187074430286930435642552406388667953361841097244392551523742725827601531 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 69375141069588314180950413589806669686360459257468383777988298520861151278348 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 42204732527508609503682200712771892926372619566828421520284577948345290221323 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 52732516334836939584358656127363663821295834804137120577535943488201951681386 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3122224818711782734332110255193791021707807937261835106868047884966698013482 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 10955693527262006405137343905602235355709712279495477567056363662193640402421 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 30858641971341075995606733911789087001767200396956376573389720432692595936883 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 17613828206273690183404747305600275374830908134113763947996473876357433228165 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 107462716031878671397951301748183464169642989705394399361741354855338449246637 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 46012568974015166944295012746523322769799543019367644616650313795223877249837 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 79945225805288997533400303281026103355736688808045835348892354082392842492591 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 33784610029684677441834308821795147815495423984995771896389596443361843992172 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 115775048670804536166230658973790250327611432519473740619131135239155936744580 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 29267964617731985647099372806303429684853147203076324987076127373090540604587 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 114923591317254637606228058840095901695132629428361075636252009510476060730574 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 24894296904976562991285089738052359013030565096869173291996735674975173499712 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 87708254067085826426314444920040880295354353436889710308744947940960737316623 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_dev 32184026390930490464312557970989468274835900286617352366441696012238218507262 None
Waiting for it to complete...
Another command (pid=1427444) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod 47718456108352712515105039730374480629049403381587151666577846037618680201628 None
---- STDERR ----
Another command (pid=1425254) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 72149408659446425333392759629202114652930899261508425827120452045464954809915 None
---- STDERR ----
Another command (pid=1426860) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_rma 97120845754150580865873706968485419257498946404910008832344755176856921363741 None
---- STDERR ----
Another command (pid=1428450) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 31108605072346916366944336565277956681874557072721000939764386040924156404073 None
---- STDERR ----
Another command (pid=1425502) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_dev 89394515712640239494817613642738007484395090994700195572262074015729639914028 None
---- STDERR ----
Another command (pid=1427121) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod 12195601762064118166094554177098609632147512370615979592163177492450679905213 None
---- STDERR ----
Another command (pid=1428664) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 91409941400587310334448385195500176990291844420781341907492060895140265460895 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_rma 61119124171611811444864618394330539194371842676274000464308490922841122542755 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3652467007781963140779474443358669515987124381150074007328289161089017275269 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_dev 100640495803398782463331422816962985364171604088046801418632770359656319190427 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod 49291934729476153936492739269431235064038884853824469554511529796564093832358 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 89302462562859175362846722707062255862123096507766965155209818462996927420770 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_rma 46071499114003538769305842562979374003261240410788561659647790496237035713459 None
---- STDERR ----
Another command (pid=1433109) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 46294097780224515146000709772399675364316966089635649797600210225186935072927 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 12930392051195340824916657440804259677820832902287621394001276863786857345033 None
cwd=/nightly/current_run/opentitan
Waiting for it to complete...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 38161253934964097124131918614775403254859367004635937834025931569786786472072 None
---- STDERR ----
Another command (pid=1432757) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 74207377691965949923240839057275943151734654583603528382923399414290497653414 None
---- STDERR ----
Another command (pid=1433348) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 64862528919169822501868618123993224431000199768032054615091170411718008630390 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_test_unlocked0 73682819097333002978248825872589066759323208949540923335405084229303201054320 None
---- STDERR ----
Another command (pid=1434227) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_dev 7510291399612307668072654487385182072434608763474932561674453086316819927949 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_rma 66624959453854051441320899285302571512860048561604608980369546706077559842616 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_test_unlocked0 81475470430231966758385491809251319311063775528010742809233718536707852350142 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_dev 88299680954884837369171179618955067922852604868014707374532844020656187766516 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_rma 88812559907026662065927683674817986867315642427590828758463279184543868178841 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_static_critical 87789051394043890670209841055689464030162970687521560892078519890031606881001 None
---- STDERR ----
Another command (pid=1437112) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_meas 101023677137466234450566188665020207255075573334282412467420179569705488516428 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_no_meas 23153288328050346378265256807207485853410265424475869457540420530102522859382 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_invalid_meas 74877427930657805287496296053514453847847917735762276612984242979132320785718 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 93743703748877978866392556375931332690919569332785324007708383883062206222925 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 76958517830958588895172130837798242580576931569885901053385072493722048346990 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_otbn 93339667739716831594377318190013457669299591388623091768019743518008935689515 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_sw 52120368068521729983149408188028069700627274731144275999875099501227789865782 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_otbn 99488584229864781930850537765585059746560042702351984765785415133472120326391 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_sw 24981782915240892494620440392142644519337808294138547982678108601324818697442 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_otbn 95024067738000755664235156751560960585150786352522761557010394995420817330080 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_sw 105564231858449251388131909562161579152583620046407029393669065128736634395863 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_otbn 35791784285935991714112343306096165835307174326861348576672588134583621981838 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_sw 45530423029295870533066352812375387942655495737699119918753844383608729559425 None
---- STDERR ----
Another command (pid=1440275) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 91745055861329862981821753292488363533802526679203013093242787663666258434265 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 112097537805890415497793476119331218373984238971990364609663611745159418038281 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 52522532392329612228555964658732224321449157969338834533847106183979314502017 None
---- STDERR ----
Another command (pid=1441361) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_smoketest_signed 50259382203649242683016862913443929106407084089410069883513396619997851842382 None
---- STDERR ----
Another command (pid=1441597) is running. Waiting for it to complete on the server (server_pid=903692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_keymgr_functest 38023489866662455817279790762532534397655918856919593138829858315408501464545 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.507s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
chip_sw_all_escalation_resets 33921941458359353637744482420740974048363721425783784670921994467445835806326 350
UVM_ERROR @ 947.512000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 947.512000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 74956693298001977053403922313166038497776017276648839781502291216713017955256 348
UVM_ERROR @ 947.589000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 947.589000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 56969165905935683067296360875604745384307070566531501168935120183220725179704 332
UVM_ERROR @ 273.318000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 273.318000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 42903907999185679595649744626073500246915416435626359208059159565042608080399 328
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 179.576000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 179.576000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
chip_sw_rstmgr_alert_info 113698704095314075433819187908612272738943926062969736334684163833363638502503 342
UVM_ERROR @ 331.949000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 331.949000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rstreqs[*]) && (reset_cause != HwReq))'
chip_sw_rstmgr_cpu_info 101292410832151449910833137345408662503743406308565375107454523345478788998863 346
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.288000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.288000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_aes_trans 47946944197966789564175233556678727732473136431243525350717673212756349273077 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.208000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_hmac_trans 5858885704534507389932886999179233936444549757375375931645464642873409465062 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.144000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.144000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_kmac_trans 98023655646803469458724779726926069673268916937856544634436053511131043863019 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.224000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.224000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_otbn_trans 105941698260549197428238937563434552344063796939505133007928418338749845409786 323
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.240000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
chip_sw_soc_proxy_smoketest 47949627508622919638770865734065212229728541986057916471146569642464204502939 321
UVM_ERROR @ 155.840000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 155.840000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *
chip_sw_soc_proxy_external_wakeup 35399756860413116123650030976889566269432490705625275571477379884033407085839 319
UVM_ERROR @ 157.403000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.403000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns *
chip_sw_soc_proxy_gpios 21877587053499472820552195922641448950011722313600036903980195808867398242333 319
UVM_ERROR @ 155.042000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 155.042000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec
chip_sw_aon_timer_irq 72863233092921740142226759701157733244433257730331220698254051241214994032331 320
UVM_ERROR @ 600.120000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4429 usec which is not in the range 404 usec and 461 usec
UVM_INFO @ 600.120000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds
chip_sw_aon_timer_wdog_bite_reset 4867339265095271336257417087059539808522834856304743259659748846023434008497 321
UVM_ERROR @ 182.899000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.899000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
chip_sw_otbn_ecdsa_op_irq_jitter_en 92628736478648478724987500297786137857783104968294359230040880249425034871976 312
UVM_FATAL @ 10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en 76033891005508112497936197019535483957844593113705141818587167945664638495353 312
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en 92862896725491245299795375367796155685810032129990051675707367203924941739489 312
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en 103728995949155221725939870776686802156893160154937010140587307249773329888606 312
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en 97784540862951922055078609698777082971066639187928352919213653087096689933456 312
UVM_FATAL @ 10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 23022699322655915433850989524372996298617786875859428788670045695991436244349 312
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en_reduced_freq 103564706959945095988793096182866986563182396843409421998011763270315515135551 312
UVM_FATAL @ 10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en_reduced_freq 52213978572382898304352063775097984698352097954130416020124432420904796467309 312
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 71315676082707814928949766479796397240166432948002902554006418508645890371282 312
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 84288896553685147156121734831791577335113189191558213240614022556546425537181 312
UVM_FATAL @ 10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 96671030445080406111015165456559582547605651010945524132235581407380711080432 312
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_edn_concurrency_reduced_freq 31338446076162867814821115417447408229660796524110693898014070739041601423275 312
UVM_FATAL @ 10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired
chip_sw_rv_core_ibex_nmi_irq 92970959688725309668734834103885583074848482061072060939128143928391438508915 322
UVM_ERROR @ 271.295000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 271.295000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP
chip_sw_keymgr_dpe_key_derivation 38985063421461526382168963330558092453497428975433716763716533403319018392945 340
UVM_ERROR @ 306.959000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2779832717764170329951527895458127828629986918506504817636604349706871834090469745136193299243973662184886552504334589558956572441991452681618462557428828 [0x35138a0eaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3b3453aff7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 306.959000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_prod 110444308988567252317241494316439667378265670391900789927162160192530222726301 340
UVM_ERROR @ 307.000000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (9339479667657088026028921587553208994601977740335756823501559399237453542830509190342139080132358206860182247072598963062465183651669103190415716332690524 [0xb2526cf9aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd33404dc087f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 307.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_jtag_csr_rw 31021429273120048263907577926813042252827772098724089257682817588522904018089 5950
UVM_ERROR @ 117.016000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: 'h30480000 a_data: 'h76fe3d07 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h0 a_user: 'h26920 d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 99349676253448464827863345983071332750832147535982567832336971457555808297701 5950
UVM_ERROR @ 117.029000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41716) { a_addr: 'h30480000 a_data: 'h2524cd81 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h0 a_user: 'h2691c d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *
chip_sw_dma_abort 67040188091188849269263042930313297174461538458616158048536422352321437636937 325
UVM_ERROR @ 211.728000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 211.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---