Simulation Results: edn/edn1

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 84.12 %
  • assert
  • 97.14 %
  • func
  • 78.99 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 90.46 %
  • toggle
  • 95.70 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 0.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.230s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.070s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.070s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.070s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.710s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 0.000us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 0.000us 1 1 100.00
edn_disable_auto_req_mode 0.860s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.620s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.360s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.360s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 0.000us 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.190s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 0.000us 1 1 100.00
edn_csr_rw 0.760s 0.000us 1 1 100.00
edn_csr_aliasing 0.930s 0.000us 1 1 100.00
edn_same_csr_outstanding 1.190s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.970s 0.000us 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 0.000us 1 1 100.00
edn_sec_cm 2.270s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.970s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 92.660s 0.000us 1 1 100.00