Simulation Results: i2c

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.82 %
  • code
  • 81.15 %
  • assert
  • 95.98 %
  • func
  • 80.34 %
  • line
  • 96.29 %
  • branch
  • 92.05 %
  • cond
  • 84.89 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 14.330s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.120s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.100s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.990s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.740s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 0.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.930s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 750.230s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 865.180s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.640s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 194.710s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 48.120s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.960s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 3.330s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 6.300s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 56.750s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.800s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.690s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.970s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 46.140s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.400s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 11.860s 0.000us 1 1 100.00
i2c_target_intr_smoke 2.990s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.280s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.010s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 8.010s 0.000us 1 1 100.00
i2c_target_stress_rd 11.860s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 2.850s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.300s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 4.390s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.120s 0.000us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.840s 0.000us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.260s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.320s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 865.180s 0.000us 1 1 100.00
i2c_host_perf_precise 1.480s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.800s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 7.420s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.860s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.860s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.290s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.290s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.680s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.750s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.670s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.710s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.710s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 0.990s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.780s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.680s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 0.990s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.780s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.980s 0.000us 1 1 100.00
i2c_tl_intg_err 1.100s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.100s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 26.840s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.050s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 8.390s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 98739066301850101341226529149405098004958367072992476283530263825375461147320 86
UVM_ERROR @ 54550581 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 54550581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 72946083435488088117497906521296189396316003119302762429458121477229302156053 155
UVM_ERROR @ 12981255730 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 12981255730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 24069135957111860055137014832244027802737233558850913210870230184978870520079 94
UVM_ERROR @ 678770450 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 678770450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 80679633283483409127685277053981869865205645946788785380405901010232669445428 81
UVM_ERROR @ 23858521 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 23858521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 110546160429399762696070394148183417573869681204405498348537458723391231982563 84
UVM_ERROR @ 1116524039 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1116524039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 41188355627277421712222983474578119954285036497364631302583799336692412158856 78
UVM_ERROR @ 136367070 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 64 [0x40])
UVM_INFO @ 136367070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 58195772160778226136138225602141479071809782148344318850488844915759348870999 94
UVM_ERROR @ 3808947951 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3808947951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 51332135454719847772724759332845661904972647499444216542073318076017223217658 78
UVM_ERROR @ 1538488639 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1538488639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---