Simulation Results: kmac/unmasked

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.54 %
  • code
  • 88.24 %
  • assert
  • 97.75 %
  • func
  • 91.63 %
  • line
  • 97.22 %
  • branch
  • 94.78 %
  • cond
  • 91.35 %
  • toggle
  • 100.00 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 39.920s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.880s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.020s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.420s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.060s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.230s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.020s 0.000us 1 1 100.00
kmac_csr_aliasing 3.060s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.740s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.230s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1001.780s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 410.740s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1173.390s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 32.830s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 16.830s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 10.950s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 143.210s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 94.180s 0.000us 1 1 100.00
kmac_test_vectors_kmac 2.350s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 2.090s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 234.600s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 196.240s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 162.120s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 82.660s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 143.850s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 8.570s 0.000us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 37.930s 0.000us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 16.510s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 9.460s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 12.070s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.630s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 786.640s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.730s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.040s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.610s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.610s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.880s 0.000us 1 1 100.00
kmac_csr_rw 1.020s 0.000us 1 1 100.00
kmac_csr_aliasing 3.060s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.860s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.880s 0.000us 1 1 100.00
kmac_csr_rw 1.020s 0.000us 1 1 100.00
kmac_csr_aliasing 3.060s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.860s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.230s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.230s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.230s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.230s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.010s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.040s 0.000us 1 1 100.00
kmac_sec_cm 40.400s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.040s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.630s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 39.920s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 234.600s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.230s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 40.400s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 40.400s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 40.400s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 39.920s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.630s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 40.400s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 110.100s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 39.920s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 18.210s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19)
kmac_sideload_invalid 51434164945469475305940169376767043185911638945695738778743058381792010223546 97
UVM_FATAL @ 10377855937 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x96da9000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10377855937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 88189642037978717404669285088758896167592792436287606300467327875948949442977 122
UVM_ERROR @ 1089090593 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1089090593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---