Simulation Results

Simulation Results: rv_dm/use_dmi_interface

12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.59 %

code
73.33 %

assert
96.09 %

func
72.34 %

line
90.64 %

branch
75.21 %

cond
76.74 %

toggle
70.92 %

FSM
53.12 %

Validation stages

V1		96.77%
V2		75.00%
V2S		83.33%
V3		0.00%
unmapped		0.00%

30/31 passed

96.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	2.570s	0.000us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.330s	0.000us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	0.860s	0.000us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	4.510s	0.000us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.050s	0.000us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	13.140s	0.000us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	2.840s	0.000us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	25.950s	0.000us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	45.120s	0.000us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.140s	0.000us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.020s	0.000us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.360s	0.000us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.810s	0.000us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	0.750s	0.000us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	1.000s	0.000us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.960s	0.000us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.770s	0.000us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.140s	0.000us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.850s	0.000us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	0.910s	0.000us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.360s	0.000us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.860s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.220s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.450s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	54.090s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.340s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.820s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.340s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.450s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.750s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.790s	0.000us	1	1	100.00

21/28 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	2.570s	0.000us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	0.870s	0.000us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.750s	0.000us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	1.040s	0.000us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.630s	0.000us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	150.750s	0.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	49.870s	0.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	385.310s	0.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	542.710s	0.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.940s	0.000us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	4.600s	0.000us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	0.870s	0.000us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.640s	0.000us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm_rand_reset	58.520s	0.000us	1	1	100.00
	rv_dm_tap_fsm	7.200s	0.000us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	1.300s	0.000us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	0.940s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	1.020s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	1.860s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	1.860s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.340s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	1.220s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.450s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	5.760s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.340s	0.000us	1	1	100.00
	rv_dm_csr_hw_reset	1.220s	0.000us	1	1	100.00
	rv_dm_csr_rw	1.450s	0.000us	1	1	100.00
	rv_dm_same_csr_outstanding	5.760s	0.000us	1	1	100.00

V2S

10/12 passed

83.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_tl_intg_err	6.660s	0.000us	1	1	100.00
	rv_dm_sec_cm	1.460s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	6.660s	0.000us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.600s	0.000us	1	1	100.00
	rv_dm_debug_disabled	1.040s	0.000us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.600s	0.000us	1	1	100.00
	rv_dm_debug_disabled	1.040s	0.000us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	2.570s	0.000us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	1.210s	0.000us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.930s	0.000us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.930s	0.000us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	1.210s	0.000us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	2.780s	0.000us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	157.150s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	103302291132584424554858056063918369702838630642080058719446817489228141662112	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	90937914187090991532739192210239950694233746458155585450068987408287725849246	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	13392886723450930323504325251502686047937265957170819761880052731323158824971	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	87337022108811748820164650048585559674389089117383962247846589839030746557967	86	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	83892589326719920171860911915801387852823535663557046802098791979208241571936	77	UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	6401729038296602661103967336696910598145584474849400980789612540622581669167	77	UVM_ERROR @ 97559428 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 97559428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89223586336435760366447041047710429015938888227402727896386761671714163779377	79	UVM_ERROR @ 589632537 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 589632537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	86017736079729359139669437870186284158197699088828015042680340115481555049112	84	UVM_ERROR @ 1562991437 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 1562991437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	64082096717525301506069540575965866509850619598925475663198126709264968161715	77	UVM_ERROR @ 74191947 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) UVM_INFO @ 74191947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	104576381510872808586326577938477710560423571583010020934913751224579593865018	77	UVM_ERROR @ 254282039 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1579967615 [0x5e2c647f] vs 0 [0x0]) UVM_INFO @ 254282039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])
	rv_dm_buffered_enable	55900049830946306696828030589957257597060398807466805198494286247982156960865	84	UVM_ERROR @ 214452126 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1]) UVM_INFO @ 214452126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---