Simulation Results: sram_ctrl/ret

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.62 %
  • code
  • 91.38 %
  • assert
  • 95.79 %
  • func
  • 93.69 %
  • line
  • 98.05 %
  • branch
  • 95.45 %
  • cond
  • 91.80 %
  • toggle
  • 90.66 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.510s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.800s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.330s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.730s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.900s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.730s 0.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.560s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.590s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 635.870s 0.000us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 182.950s 0.000us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 38.430s 0.000us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 73.480s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.920s 0.000us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 561.650s 0.000us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.400s 0.000us 1 1 100.00
sram_ctrl_partial_access_b2b 167.630s 0.000us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.060s 0.000us 1 1 100.00
sram_ctrl_throughput_w_partial_write 12.030s 0.000us 1 1 100.00
sram_ctrl_throughput_w_readback 4.180s 0.000us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 598.400s 0.000us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.900s 0.000us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2391.730s 0.000us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.820s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.790s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.790s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.730s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.840s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 0.000us 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sram_ctrl_csr_aliasing 0.730s 0.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.140s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
sram_ctrl_tl_intg_err 1.480s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.480s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 598.400s 0.000us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 598.400s 0.000us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.850s 0.000us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 561.650s 0.000us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 561.650s 0.000us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 561.650s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.920s 0.000us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 1.040s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.140s 0.000us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.940s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.510s 0.000us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.510s 0.000us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 561.650s 0.000us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.920s 0.000us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.510s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.790s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.140s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 35005966362560612933249481574766765287153393752879736619806813798262168245376 104
Offending 'reqfifo_rvalid'
UVM_ERROR @ 56986700 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 56986700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 49257102206245446370790990604583810314134582996508454889681866278643619029415 101
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 950975ps failed at 950975ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 1885318 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1885318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]