Simulation Results: xbar_main

 
12/03/2026 16:05:50 DVSim: v1.14.2 sha: ee1b0f6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.19 %
  • code
  • 98.86 %
  • assert
  • 98.22 %
  • func
  • 70.49 %
  • line
  • 100.00 %
  • branch
  • 99.83 %
  • cond
  • 95.63 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.44%
Testpoint Test Max Runtime Sim Time Pass Total %
xbar_smoke 1 1 100.00
xbar_smoke 11.890s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
xbar_base_random_sequence 1 1 100.00
xbar_random 155.480s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.910s 0.000us 1 1 100.00
xbar_smoke_large_delays 187.130s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 202.840s 0.000us 1 1 100.00
xbar_random_zero_delays 34.420s 0.000us 1 1 100.00
xbar_random_large_delays 522.010s 0.000us 1 1 100.00
xbar_random_slow_rsp 337.920s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 54.270s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 65.190s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 33.180s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 65.190s 0.000us 1 1 100.00
xbar_all_access_same_device 1 2 50.00
xbar_access_same_device 163.530s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 2178.200s 0.000us 0 1 0.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 49.650s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 229.820s 0.000us 1 1 100.00
xbar_stress_all_with_error 151.120s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 304.000s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 501.070s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
xbar_access_same_device_slow_rsp 6732395576253793108720972350054993745965997443033929474533298962677520369726 183
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---