Simulation Results: hmac

 
16/03/2026 16:04:31 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.85 %
  • code
  • 94.07 %
  • assert
  • 96.70 %
  • func
  • 42.78 %
  • line
  • 98.45 %
  • branch
  • 95.70 %
  • cond
  • 93.87 %
  • toggle
  • 100.00 %
  • FSM
  • 82.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.800s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.650s 0.000us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.760s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.580s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.770s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.820s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.760s 0.000us 1 1 100.00
hmac_csr_aliasing 3.770s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 11.690s 0.000us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 29.390s 0.000us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 183.730s 0.000us 1 1 100.00
hmac_test_sha384_vectors 356.350s 0.000us 1 1 100.00
hmac_test_sha512_vectors 433.440s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.310s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 9.480s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 0.000us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.050s 0.000us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 156.210s 0.000us 1 1 100.00
error 1 1 100.00
hmac_error 0.670s 0.000us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 74.180s 0.000us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.800s 0.000us 1 1 100.00
hmac_long_msg 11.690s 0.000us 1 1 100.00
hmac_back_pressure 29.390s 0.000us 1 1 100.00
hmac_datapath_stress 156.210s 0.000us 1 1 100.00
hmac_burst_wr 1.050s 0.000us 1 1 100.00
hmac_stress_all 616.500s 0.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.800s 0.000us 1 1 100.00
hmac_long_msg 11.690s 0.000us 1 1 100.00
hmac_back_pressure 29.390s 0.000us 1 1 100.00
hmac_datapath_stress 156.210s 0.000us 1 1 100.00
hmac_wipe_secret 74.180s 0.000us 1 1 100.00
hmac_test_sha256_vectors 183.730s 0.000us 1 1 100.00
hmac_test_sha384_vectors 356.350s 0.000us 1 1 100.00
hmac_test_sha512_vectors 433.440s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.310s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 9.480s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 0.000us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.800s 0.000us 1 1 100.00
hmac_long_msg 11.690s 0.000us 1 1 100.00
hmac_back_pressure 29.390s 0.000us 1 1 100.00
hmac_datapath_stress 156.210s 0.000us 1 1 100.00
hmac_burst_wr 1.050s 0.000us 1 1 100.00
hmac_error 0.670s 0.000us 1 1 100.00
hmac_wipe_secret 74.180s 0.000us 1 1 100.00
hmac_test_sha256_vectors 183.730s 0.000us 1 1 100.00
hmac_test_sha384_vectors 356.350s 0.000us 1 1 100.00
hmac_test_sha512_vectors 433.440s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.310s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 9.480s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 0.000us 1 1 100.00
hmac_stress_all 616.500s 0.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 616.500s 0.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 0.000us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.580s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.220s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.220s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.650s 0.000us 1 1 100.00
hmac_csr_rw 0.760s 0.000us 1 1 100.00
hmac_csr_aliasing 3.770s 0.000us 1 1 100.00
hmac_same_csr_outstanding 0.930s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.650s 0.000us 1 1 100.00
hmac_csr_rw 0.760s 0.000us 1 1 100.00
hmac_csr_aliasing 3.770s 0.000us 1 1 100.00
hmac_same_csr_outstanding 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 0.000us 1 1 100.00
hmac_tl_intg_err 2.850s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.850s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.800s 0.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.960s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 171.800s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.620s 0.000us 1 1 100.00