Simulation Results: kmac/masked

 
16/03/2026 16:04:31 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.46 %
  • code
  • 90.14 %
  • assert
  • 95.96 %
  • func
  • 94.27 %
  • line
  • 98.67 %
  • branch
  • 96.20 %
  • cond
  • 93.28 %
  • toggle
  • 99.86 %
  • FSM
  • 62.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 21.960s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.890s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.560s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.050s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.710s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.050s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.890s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.210s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 534.920s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 859.390s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1811.980s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 1959.320s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 35.070s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 12.980s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 152.010s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 1885.480s 0.000us 1 1 100.00
kmac_test_vectors_kmac 2.820s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 2.020s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 323.930s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 98.850s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 37.760s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 70.000s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 351.490s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 8.780s 0.000us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 6.350s 0.000us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 17.400s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 23.110s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 6.900s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.510s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 74.770s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.790s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.020s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.390s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.390s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.890s 0.000us 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.050s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.800s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.890s 0.000us 1 1 100.00
kmac_csr_rw 0.820s 0.000us 1 1 100.00
kmac_csr_aliasing 3.050s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.800s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.510s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 3.380s 0.000us 1 1 100.00
kmac_sec_cm 37.810s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.380s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.510s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 21.960s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 323.930s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.770s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 37.810s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 37.810s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 37.810s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 21.960s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.510s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 37.810s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 283.820s 0.000us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 21.960s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 72.700s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_mubi 58451978025415960277199016223862559681664841825110205107701856927368176356265 247
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---