Simulation Results: mbx

 
16/03/2026 16:04:31 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 90.18 %
  • assert
  • 96.86 %
  • func
  • 74.12 %
  • block
  • 95.74 %
  • line
  • 96.02 %
  • branch
  • 88.65 %
  • toggle
  • 85.88 %
Validation stages
V1
87.50%
V2
81.25%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 28.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 105.000s 0.000us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 57.000s 0.000us 1 1 100.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 9.000s 0.000us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 10.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 0.000us 1 1 100.00
mbx_csr_rw 2.000s 0.000us 1 1 100.00
mbx_csr_aliasing 2.000s 0.000us 1 1 100.00
mbx_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 3.000s 0.000us 1 1 100.00
mbx_tl_intg_err 3.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_imbx_oob 62078064731400295854621717863146526124848024024878825049138561880553472399866 125
UVM_ERROR @ 3986636763 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 3986636763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 102732359095286787941603022634305338896002978835184100634286731490492817453941 85
UVM_ERROR @ 4878455 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@15845) { a_addr: 'hc92c1030 a_data: 'ha0d9db79 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'h9b a_opcode: 'h1 a_user: 'h25a29 d_param: 'h0 d_source: 'h9b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4878455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 50900792236951189492050846711353221688456059008438889859033662208292098070098 86
UVM_ERROR @ 5645894 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@18365) { a_addr: 'he72afbf4 a_data: 'h6b226d8e a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'ha9 a_opcode: 'h1 a_user: 'h245d8 d_param: 'h0 d_source: 'ha9 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5645894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---