| V1 |
|
90.91% |
| V2 |
|
78.95% |
| V2S |
|
64.52% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 0.000us | 1 | 1 | 100.00 | |
| single_binary | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 6.000s | 0.000us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 81.000s | 0.000us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 14.000s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 0 | 1 | 0.00 | |||
| otbn_reset | 4.000s | 0.000us | 0 | 1 | 0.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 42.000s | 0.000us | 1 | 1 | 100.00 | |
| back_to_back | 0 | 1 | 0.00 | |||
| otbn_multi | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| otbn_stress_all | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_escalation | 0 | 1 | 0.00 | |||
| otbn_escalate | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 11.000s | 0.000us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 8.000s | 0.000us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 13.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 0.000us | 1 | 1 | 100.00 | |
| internal_integrity | 0 | 4 | 0.00 | |||
| otbn_alu_bignum_mod_err | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| otbn_controller_ispr_rdata_err | 4.000s | 0.000us | 0 | 1 | 0.00 | |
| otbn_mac_bignum_acc_err | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| otbn_urnd_err | 4.000s | 0.000us | 0 | 1 | 0.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 0 | 1 | 0.00 | |||
| otbn_partial_wipe | 4.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 9.000s | 0.000us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 34.000s | 0.000us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 10.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 13.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 9.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 0 | 1 | 0.00 | |||
| otbn_escalate | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 13.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 13.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 0 | 1 | 0.00 | |||
| otbn_escalate | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 13.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 10.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 4.000s | 0.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 6.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 6.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 18.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 18.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 0 | 1 | 0.00 | |||
| otbn_rf_base_intg_err | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 0 | 1 | 0.00 | |||
| otbn_rf_bignum_intg_err | 4.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 0 | 1 | 0.00 | |||
| otbn_stack_addr_integ_chk | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_call_stack_addr_integrity | 0 | 1 | 0.00 | |||
| otbn_stack_addr_integ_chk | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 0 | 1 | 0.00 | |||
| otbn_sec_wipe_err | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_data_mem_sec_wipe | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_instruction_mem_sec_wipe | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sec_wipe | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_write_mem_integrity | 0 | 1 | 0.00 | |||
| otbn_multi | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_count | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_sca | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_data_mem_sw_noaccess | 0 | 1 | 0.00 | |||
| otbn_sw_no_acc | 6.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_sideload | 0 | 1 | 0.00 | |||
| otbn_single | 5.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 261.000s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 11.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. | ||||
| otbn_single | 54894091815813887512456397663658986800359102311613090651156901908279398861891 | 124 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 56465242 PS + 27) Sampled value (27705693199164534) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 56465242 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.addv'
UVM_INFO @ 56465242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_multi | 94233102467824409973377532503590739762071772219349118705817454644114025144933 | 157 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 9258078 PS + 42) Sampled value (27705693401607286) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 9258078 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulv'
UVM_INFO @ 9258078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_reset | 44110023471467371477154138876003563275478232557602511407427322338864140411524 | 117 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 6952428 PS + 25) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 6952428 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 6952428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_escalate | 69192374394471123365210607770385158233796933004034027109010546070699183293531 | 112 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 10313058 PS + 25) Sampled value (108225365239926) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 10313058 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.shv'
UVM_INFO @ 10313058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_alu_bignum_mod_err | 96683501858123667054501867350946624834973005548091325203664281794333589372515 | 115 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 5201776 PS + 29) Sampled value (7092657510811465325) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 5201776 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulvm'
UVM_INFO @ 5201776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_controller_ispr_rdata_err | 41765893043176255856500401015193700558571007654636651246244601295559514474522 | 112 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 25716568 PS + 25) Sampled value (27705693535367275) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 25716568 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.unpk'
UVM_INFO @ 25716568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_mac_bignum_acc_err | 6658342760816352077620512278840361836033851120609087414064989761841181049799 | 111 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 4866699 PS + 25) Sampled value (27705693401607286) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 4866699 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulv'
UVM_INFO @ 4866699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_rf_bignum_intg_err | 57886658662265869133050926211833926908398151117559098189063716129040593386247 | 113 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 8564867 PS + 25) Sampled value (1815720322767735123308) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 8564867 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulvml'
UVM_INFO @ 8564867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_rf_base_intg_err | 98307836372764628226142241698300369557851936180651427880427151073817082992579 | 109 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 5482248 PS + 25) Sampled value (7092657510811465325) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 5482248 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulvm'
UVM_INFO @ 5482248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all | 37529758192496106587844483194032134146156982941049920206925036432647127891764 | 146 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 21875262 PS + 25) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4206_1.cur_cp) is an illegal value.
UVM_FATAL @ 21875262 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 21875262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 115461563017101555256527289032481786273164391664064960416799013339002947006875 | 168 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 91605514 PS + 29) Sampled value (7092657510811465324) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4208_1.cur_cp) is an illegal value.
UVM_FATAL @ 91605514 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulvl'
UVM_INFO @ 91605514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_sec_wipe_err | 29576802901408856397995351919362105224942480531878717006693074303976886802788 | 112 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 17749843 PS + 33) Sampled value (27705693518851634) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 17749843 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn2'
UVM_INFO @ 17749843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_urnd_err | 54218692518723491480755411379456800191630860225762629358988575444921913507925 | 107 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 7959437 PS + 27) Sampled value (27705693450625899) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 7959437 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.pack'
UVM_INFO @ 7959437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_sw_no_acc | 52475434417117206126083956821496335176800291926372421270981733955329234788628 | 108 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 25107901 PS + 23) Sampled value (7092657510811465324) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 25107901 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.mulvl'
UVM_INFO @ 25107901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stack_addr_integ_chk | 16044463375126175499964606672357416814540358970384268212119369287552631896636 | 110 |
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_env_cov.sv, Line: 733):(Time: 64338892 PS + 45) Sampled value (27705693518851633) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@4205_1.cur_cp) is an illegal value.
UVM_FATAL @ 64338892 ps: (otbn_env_cov.sv:2538) [uvm_test_top.env.cov] Unknown encoding () for instruction `bn.trn1'
UVM_INFO @ 64338892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed | ||||
| otbn_partial_wipe | 24241293379954015997461890440496475928813949188841642867464479212453331271415 | 115 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 13694303 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 13694303 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 13694303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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