Simulation Results: rom_ctrl/64kb

 
16/03/2026 16:04:31 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.55 %
  • code
  • 99.18 %
  • assert
  • 96.80 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 99.75 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.390s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.750s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.620s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.330s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.520s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.870s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.620s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.520s 0.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.430s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.680s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.590s 0.000us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 24.130s 0.000us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.870s 0.000us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.050s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.050s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.050s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.750s 0.000us 1 1 100.00
rom_ctrl_csr_rw 7.620s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.520s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.310s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.750s 0.000us 1 1 100.00
rom_ctrl_csr_rw 7.620s 0.000us 1 1 100.00
rom_ctrl_csr_aliasing 6.520s 0.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.310s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.960s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 92.990s 0.000us 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.390s 0.000us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.390s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.390s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 92.990s 0.000us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
rom_ctrl_kmac_err_chk 11.870s 0.000us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.970s 0.000us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.960s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 450.440s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 68.710s 0.000us 1 1 100.00