Simulation Results: clkmgr

 
17/03/2026 16:08:08 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.97 %
  • code
  • 68.16 %
  • assert
  • 88.22 %
  • func
  • 71.54 %
  • line
  • 81.43 %
  • branch
  • 86.59 %
  • cond
  • 76.67 %
  • toggle
  • 96.13 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
47.37%
V2S
35.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.940s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.890s 0.000us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.550s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.760s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.960s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.760s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.770s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.040s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.810s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.940s 0.000us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.740s 0.000us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.600s 0.000us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.740s 0.000us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.830s 0.000us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.840s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.040s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.040s 0.000us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 0.000us 1 1 100.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.760s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 0.000us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 0.000us 1 1 100.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.760s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.300s 0.000us 0 1 0.00
clkmgr_tl_intg_err 0.640s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.660s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.640s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.740s 0.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.600s 0.000us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.010s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.460s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.300s 0.000us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.700s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.300s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.670s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.670s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 114090180411374995679870092135976443635429923362933508194412962178575702980165 80
UVM_ERROR @ 8368748 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 8368748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 94841883724217749125827717184839269798283316631657573031290892418220922226532 77
UVM_ERROR @ 1751847 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 1751847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 67654222472454084733572455336040871026875277021525101778151245661861835231495 79
UVM_ERROR @ 3700828 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 3700828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 107774233523290071716614771253062251299778089701900008494062221787447573665952 77
UVM_ERROR @ 22854749 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 22854749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 89399495885380057389585630019513702898136328420580564263176376919913629123791 74
UVM_ERROR @ 3373561 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en
UVM_INFO @ 3373561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 74477353065352508552624594235644943212124253317092202619876099330005901639883 132
UVM_ERROR @ 60998990 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 60998990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 27232439187749018523816006482518378468827537981089608566681072529323912762611 75
UVM_ERROR @ 7570428 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 7570428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 83880583852912789983303361023412143611884717605327751870572000183075740514440 85
UVM_ERROR @ 7553650 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 7553650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 95737446872691385198289894769008201660284716895166092143406681830989478559060 75
UVM_ERROR @ 24358588 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 24358588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_csr_rw 67606587193680111723318513826371652926475034499520848065980763790759035267774 75
UVM_ERROR @ 5392387 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 5392387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 79158515467495817351001704905707520305949954998132094516329979421715226436102 82
UVM_ERROR @ 14022590 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 14022590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 28829631940418876607974138273977620396873902537639985311643906093400333546437 75
UVM_ERROR @ 3856387 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 3856387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 111098514638511441342051881967308149760055725814951874450466497369308864703614 76
UVM_ERROR @ 13053687 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x45cb7d24 read out mismatch
UVM_INFO @ 13053687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---