Simulation Results: i2c

 
17/03/2026 16:08:08 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.66 %
  • code
  • 81.51 %
  • assert
  • 95.98 %
  • func
  • 79.49 %
  • line
  • 96.41 %
  • branch
  • 92.41 %
  • cond
  • 85.04 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 20.370s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 15.180s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.790s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.900s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.030s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.820s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 1.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.710s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 516.870s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 40.720s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.610s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 49.020s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 57.080s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.790s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 7.400s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 4.620s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 25.490s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 6.840s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.060s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.750s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 685.850s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.240s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 10.980s 0.000us 1 1 100.00
i2c_target_intr_smoke 4.210s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.290s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.720s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 419.550s 0.000us 1 1 100.00
i2c_target_stress_rd 10.980s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 21.710s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.220s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.860s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.510s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.460s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.180s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.280s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 40.720s 0.000us 1 1 100.00
i2c_host_perf_precise 24.130s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 6.840s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.770s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.640s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.590s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.080s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 2.580s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.550s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.630s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.630s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.790s 0.000us 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 1.030s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.790s 0.000us 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 1.030s 0.000us 1 1 100.00
i2c_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.850s 0.000us 1 1 100.00
i2c_tl_intg_err 1.600s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.600s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 3.550s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.020s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.850s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 7260674231855769263246939392025241948939614792715363372207627266354072577525 86
UVM_ERROR @ 9666927 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 9666927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 55114756365673025718252897609499006567864196320280462568157163523210517738501 85
UVM_ERROR @ 64597413 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 64597413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_stress_all 30834215880617205806165202954344054126602645650251300663626349014561397724528 147
UVM_ERROR @ 11847501305 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13825594
i2c_host_mode_toggle 17212322397651830641513573393301266345915175828190926135214424326623448907939 85
UVM_ERROR @ 299354765 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8193
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 110164967007115769180885327658090419941465554509652297382622114056621157985549 84
UVM_ERROR @ 1621337544 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1621337544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 43310053794133587190840218891965537745583629906854617907476628758881172661816 78
UVM_ERROR @ 503454379 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 503454379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 55690810796935672473434391111533239823066818751617037279708034157763698158914 79
UVM_FATAL @ 10083097551 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10083097551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 47312635305370027179841820908305080394932444854324688549738647009814424561019 86
UVM_ERROR @ 674782655 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 674782655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---