Simulation Results: keymgr

 
17/03/2026 16:08:08 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.84 %
  • code
  • 95.40 %
  • assert
  • 97.49 %
  • func
  • 61.64 %
  • line
  • 98.82 %
  • branch
  • 97.76 %
  • cond
  • 94.48 %
  • toggle
  • 95.24 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.610s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 9.490s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.820s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.700s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.250s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 8.870s 0.000us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.000s 0.000us 1 1 100.00
keymgr_sideload_kmac 4.470s 0.000us 1 1 100.00
keymgr_sideload_aes 10.480s 0.000us 1 1 100.00
keymgr_sideload_otbn 18.630s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.400s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.560s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.410s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.030s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.580s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.130s 0.000us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 9.680s 0.000us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.850s 0.000us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.790s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.680s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.680s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.700s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.990s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.010s 0.000us 1 1 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.700s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 4.580s 0.000us 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.770s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 5.100s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.580s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.770s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 8.870s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_random 9.490s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_random 9.490s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.980s 0.000us 1 1 100.00
keymgr_random 9.490s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.560s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.580s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.580s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 9.490s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.480s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.810s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.560s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.810s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.810s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.810s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.810s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 14.720s 0.000us 1 1 100.00