| V1 |
|
100.00% |
| V2 |
|
94.44% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 10.740s | 0.000us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 4.250s | 0.000us | 1 | 1 | 100.00 | |
| xbar_random_delay | 5 | 6 | 83.33 | |||
| xbar_smoke_zero_delays | 4.670s | 0.000us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 184.320s | 0.000us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 189.470s | 0.000us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 4.910s | 0.000us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 394.370s | 0.000us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 1187.090s | 0.000us | 0 | 1 | 0.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 40.010s | 0.000us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 91.710s | 0.000us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 157.290s | 0.000us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 91.710s | 0.000us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 81.270s | 0.000us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 879.920s | 0.000us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 126.250s | 0.000us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 380.850s | 0.000us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 123.570s | 0.000us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 1491.830s | 0.000us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 266.580s | 0.000us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| xbar_random_slow_rsp | 15278786618288604583034369571748094190315973083490647010152580231389780174306 | 152 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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