| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_in | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_irq | 0 | 1 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_tests | 0 | 4 | 0.00 | |||
| chip_sw_example_rom | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_smoketest_signed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 0 | 1 | 0.00 | |||
| xbar_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 18.984s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 18.984s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 0 | 1 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_timer | 0 | 1 | 0.00 | |||
| chip_sw_rv_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_sw_irq | 0 | 1 | 0.00 | |||
| chip_sw_plic_sw_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_idle_trans | 0 | 4 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0 | 7 | 0.00 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_extended_range | 0 | 8 | 0.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 0 | 1 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_sw_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_sw_rst | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_ping_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 0 | 10 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 0 | 2 | 0.00 | |||
| chip_sw_aes_enc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 0 | 2 | 0.00 | |||
| chip_sw_aes_enc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 0 | 1 | 0.00 | |||
| chip_sw_aes_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_idle | 0 | 1 | 0.00 | |||
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc | 0 | 2 | 0.00 | |||
| chip_sw_hmac_enc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 0 | 1 | 0.00 | |||
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_enc | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_cshake | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_keymgr | 0 | 1 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 0 | 1 | 0.00 | |||
| chip_sw_kmac_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_idle | 0 | 1 | 0.00 | |||
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_csrng | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_cmd | 0 | 1 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 0 | 1 | 0.00 | |||
| chip_sw_csrng_kat_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0 | 1 | 0.00 | |||
| chip_sw_csrng_edn_concurrency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0 | 2 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_op | 0 | 2 | 0.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_urnd_entropy | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_idle | 0 | 1 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0 | 1 | 0.00 | |||
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_access | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 1 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_scrambled_access | 0 | 2 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 0 | 4 | 0.00 | |||
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_entropy | 0 | 4 | 0.00 | |||
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 0 | 6 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_prim_tl_access | 0 | 1 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 0 | 7 | 0.00 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_gpios | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_rnd | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_address_translation | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_address_translation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 0 | 14 | 0.00 | |||
| chip_sw_aes_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_hmac_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otbn_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_plic_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_timer_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_functest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 0 | 4 | 0.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_volatile_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 0 | 1 | 0.00 | |||
| xbar_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_delay | 0 | 6 | 0.00 | |||
| xbar_smoke_zero_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke_large_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_zero_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_large_delays | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_random_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_unmapped_address | 0 | 2 | 0.00 | |||
| xbar_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_cases | 0 | 2 | 0.00 | |||
| xbar_error_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_all_access_same_device | 0 | 2 | 0.00 | |||
| xbar_access_same_device | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_access_same_device_slow_rsp | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_all_hosts_use_same_source_id | 0 | 1 | 0.00 | |||
| xbar_same_source | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all | 0 | 2 | 0.00 | |||
| xbar_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_with_reset | 0 | 2 | 0.00 | |||
| xbar_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| xbar_stress_all_with_reset_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 0 | 1 | 0.00 | |||
| chip_sw_aes_masking_off | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 20 | 0.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_kat_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_ast_rng_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_plic_all_irqs_10 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_dma_inline_hashing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_dma_abort | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_mbx_smoketest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | ||||
| default | None | None |
Job timed out after 60 minutes
|
|
| xbar_build_mode | None | None |
Job timed out after 60 minutes
|
|
| Job returned non-zero exit code | ||||
| cover_reg_top | None | None |
recompiling module tb
All of 630 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 154.012 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| chip_padctrl_attributes | 56445123546930969111058406274386362043759885135257717427661525287201615608497 | None |
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:48 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
|
|
| Job killed most likely because its dependent job failed. | ||||
| chip_tl_errors | 6473994388647840036013926398294302516385203546992900708385148425172083846395 | None | ||
| chip_prim_tl_access | 8700642445100577494222393912882768423788800167232009185377203004088836033453 | None | ||
| chip_rv_dm_lc_disabled | 74103122990888227283029533870904139865802427107876034626338845018266834779186 | None | ||
| chip_csr_bit_bash | 26834703319033183595412378698427359913626041749043830939138381341763544047765 | None | ||
| chip_csr_aliasing | 82931643850613846200868159630975723067505273240333613021865231264913969708893 | None | ||
| chip_same_csr_outstanding | 37254763388688648574575734908045214806981757447230013491978830660875685668552 | None | ||
| chip_sw_example_rom | 103091230320981891469322848541364915752164777250193634439912904169157440980219 | None | ||
| chip_sw_example_manufacturer | 113685793693991355809373480007698520953076390332584443454436031669023765955591 | None | ||
| chip_sw_example_concurrency | 103066386940906334651181428052699387471781585098663973722408153465792455964570 | None | ||
| chip_sw_all_escalation_resets | 104640475917215287049705202597044163371354653640528418254583577657209214996329 | None | ||
| chip_sw_rstmgr_rst_cnsty_escalation | 69683328029679258390197069827429654668924555027603463657485340200062613760760 | None | ||
| chip_sw_data_integrity_escalation | 44624158418531654936695549207303452374134533004013806216905859540834535738549 | None | ||
| chip_sw_sleep_pin_wake | 77473638516784506645416188005299591188941991703334898494661532599880358160684 | None | ||
| chip_sw_sleep_pin_retention | 57838757982872355596969404846330347716442294465967469837570123219028033667454 | None | ||
| chip_sw_uart_tx_rx | 23969222267885843875363009509936384591825144989264940896954252342865909046638 | None | ||
| chip_sw_uart_tx_rx_bootstrap | 109680243192977881420891409078032386868475539190621160257953590510963558259479 | None | ||
| chip_sw_inject_scramble_seed | 51680397904296048096295585737582065357864952066057901247599819621132343675237 | None | ||
| chip_sw_exit_test_unlocked_bootstrap | 99592405808185578970986929853106115061407965006464083852210765324032629820818 | None | ||
| chip_sw_uart_rand_baudrate | 88829770298119353685879759169393825600723585323276196265589511247512434405513 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 94750861952321576004554344578119046908605865618681682713545137488026641139708 | None | ||
| chip_sw_i2c_host_tx_rx | 25264235253523221466492101364479497971390779081080623854802705293528386091697 | None | ||
| chip_sw_i2c_device_tx_rx | 59184133473530105967663277311856520435461141896460334716647115290172024914766 | None | ||
| chip_sw_spi_device_tpm | 89700336833753073649005769206471517177588006961198564456521309729363674180169 | None | ||
| chip_sw_spi_host_tx_rx | 71064379307944676948240513865788800887877251419959618632212552275105303990095 | None | ||
| chip_sw_spi_device_pass_through | 72920813756458483737491942261969888758127826235538026584492517972779428808915 | None | ||
| chip_sw_spi_device_pass_through_collision | 32610112261434207485754234215540331835242752078773676610051366692681186404750 | None | ||
| chip_sw_gpio | 28165829376309916470335402724608930788601897759405539133578801084500977548185 | None | ||
| chip_sw_kmac_entropy | 61358246248194903260559196112095709447299827843433430723687218283041809972888 | None | ||
| chip_sw_lc_ctrl_otp_hw_cfg | 94430460494270802537363559373346605695542610746632068564448226577077763470176 | None | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 30535607064387531596595205940380738985771527394526446038192162950595392735683 | None | ||
| chip_sw_otp_ctrl_lc_signals_dev | 41580717677727394997150770438588348020161394043358594910998325352819577354994 | None | ||
| chip_sw_otp_ctrl_lc_signals_prod | 39227633147139654308284776411328563757316981684397692019802344008130456519999 | None | ||
| chip_sw_otp_ctrl_lc_signals_rma | 60612538663833628987216590876453107476015656748930614781023035400679609668237 | None | ||
| chip_sw_otp_ctrl_vendor_test_csr_access | 26760823028243297277298806713598707269266764227446518622298839477780149530569 | None | ||
| chip_sw_otp_ctrl_escalation | 95990318634229247742588824887212431845637292536264807906711308081594728923365 | None | ||
| chip_sw_otp_ctrl_nvm_cnt | 36547185342519679748014284041898708548423468181713171032288987075228573280895 | None | ||
| chip_sw_otp_ctrl_sw_parts | 92355064560576452548141968951478289940894788091928533691135955839082459828596 | None | ||
| chip_sw_lc_ctrl_transition | 29219716143198242041026756284080444851752197736147607217913219886307047348479 | None | ||
| chip_sw_lc_ctrl_rma_to_scrap | 84679350990488628769084243599228922067964676818663167755621738094962986374575 | None | ||
| chip_sw_lc_ctrl_raw_to_scrap | 24831987132303169130700924191190939787286033817540533798879977376058158472996 | None | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 109558454426656607410468694636361988105878132285437805232438517303834628804052 | None | ||
| chip_sw_lc_ctrl_rand_to_scrap | 46700632974185868665850930904139023509772326117323309154308638275763098609260 | None | ||
| chip_sw_lc_walkthrough_dev | 63540990916099108343779824110905068126576753870235720442665679777053530130901 | None | ||
| chip_sw_lc_walkthrough_prod | 30760288080965209846002453025533440530073136472576297856001796083089758241688 | None | ||
| chip_sw_lc_walkthrough_prodend | 108962192276583562785794626565701836425518325833684360836151801849172763893104 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock | 22237375535438206939586453589440533476684769782937573233926585138696926117235 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 101234009069167649062949327528177916998461718779065494044949345840084022942257 | None | ||
| chip_sw_lc_walkthrough_rma | 69630576449588301649187403887866901306280419160042438345554148176928535490326 | None | ||
| chip_sw_lc_walkthrough_testunlocks | 21421501559889489518317697012798776883813621465617793723054511143247300468730 | None | ||
| chip_sw_rstmgr_sw_req | 84463327128082105039078090169021970963859888368493739333316458546228816344871 | None | ||
| chip_sw_rstmgr_sw_rst | 69012347846010024517462326895308969719001019652403085266818481380731060682830 | None | ||
| chip_sw_rstmgr_alert_info | 63189832006287688475722997017719861755619158766208445219005155396118118932479 | None | ||
| chip_sw_rstmgr_cpu_info | 54523303181065683833295928660233021995243943342911053622163735857805412251094 | None | ||
| chip_sw_pwrmgr_full_aon_reset | 97744084369925879133965371190536538587888854731231221448759492578056908522301 | None | ||
| chip_sw_pwrmgr_main_power_glitch_reset | 34975598873230361414974309732561474975777908031272150204935506407577128355828 | None | ||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 89396251926696053642468403413321080153149102770401898290490037128500371774722 | None | ||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 31874309753491264820782869842661724227334511969178137276005049273050794499425 | None | ||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 46199073076296725586508484759713215506722998129593981457130640159530997625712 | None | ||
| chip_sw_pwrmgr_sleep_disabled | 94045740916187417165805240027982630013359069854853027029737610700118169721412 | None | ||
| chip_sw_rv_timer_irq | 7442761082831155758942425681530459671875963679817783161633894395774580413684 | None | ||
| chip_sw_soc_proxy_smoketest | 115246048780152020174124869047339556120606452351792974265238941383074838887111 | None | ||
| chip_sw_soc_proxy_external_wakeup | 75160586464950378844799748819515817994328166798750126070937148494134241351881 | None | ||
| chip_sw_soc_proxy_gpios | 1058600767105139676562861037196289898631058047020594743100761426748517820053 | None | ||
| chip_sw_aon_timer_irq | 73746688680358589216983948077833936546713708235450669436607405849851677100966 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 50496881280679196105906057808537292625493529503535528981525575508239284990832 | None | ||
| chip_sw_aon_timer_wdog_bite_reset | 19150035222737154206262065553218134307116782622316055312716604725856127309632 | None | ||
| chip_sw_pwrmgr_wdog_reset | 71429882357878602931633169603976217104366477615729001813785964159205623510016 | None | ||
| chip_sw_aon_timer_wdog_lc_escalate | 3845766430262374898266381795348224560325757264853409892317323047896690968074 | None | ||
| chip_sw_otbn_randomness | 54897307774079970419060607060913681384924131845774887069006524807704973825345 | None | ||
| chip_sw_otbn_ecdsa_op_irq | 17053544577806228158680211715447163756902566068895634350246373126879373095340 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 60198407982467768713753074221805906716403367343305820352445919538398502763122 | None | ||
| chip_sw_otbn_mem_scramble | 105793534463650003804889875049511975960435716570035701446202391068507148415096 | None | ||
| chip_sw_rv_core_ibex_rnd | 51265431558411289861429119929929013647484962469052794551085077903244491090730 | None | ||
| chip_sw_rv_core_ibex_nmi_irq | 21506759784581119541451685879022437115011587203565073054675982007353584162911 | None | ||
| chip_sw_aes_enc | 33441156966007369540663691726381227832185675261318595836939894670648497820998 | None | ||
| chip_sw_aes_enc_jitter_en | 54385966911036187682400949412002605043627482157144157754354906379072229111001 | None | ||
| chip_sw_aes_gcm | 33864190892501199456641393431201463184153472046167960662402188565007932386176 | None | ||
| chip_sw_aes_idle | 28498270952162465726783578684017637686227324594983709370616961269330086389220 | None | ||
| chip_sw_aes_masking_off | 30353255675081726629109178679860030259462181963473035976844947070036145580702 | None | ||
| chip_sw_alert_test | 45051541615037101609142136038757194600976014173150678068901359155625181862172 | None | ||
| chip_sw_alert_handler_escalation | 16009372501959001036973854460198198720925291070545150833322360636270617105059 | None | ||
| chip_sw_alert_handler_ping_timeout | 42058255540489979623504252144214758079619931053631126194999133924695221734394 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 79683052618824432217242493464406646572797321992420935951838546703802889562509 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73907437911640227201325800075184412661028463356120306084813079117473575486387 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 70233242953004260580766624746403080718717346544318834359288106011411321923915 | None | ||
| chip_sw_alert_handler_lpg_clkoff | 94974770799535438873821540453623173263932750771479762290368647587474710852978 | None | ||
| chip_sw_alert_handler_lpg_reset_toggle | 65475587819260686467355067490594712012360205822416590415294247651664770483720 | None | ||
| chip_sw_alert_handler_entropy | 2856834147154606236906402929198064923608632975694534178448442365000716295640 | None | ||
| chip_sw_aes_entropy | 79814026741514162043271385833803376814700809800903559134438326315140589597688 | None | ||
| chip_sw_csrng_edn_concurrency | 84071425177397181297041146060770020138300544870903683924370771983148132968956 | None | ||
| chip_sw_csrng_kat_test | 45373157104036547102378539170907821939593951230862585538732310654454661852433 | None | ||
| chip_sw_csrng_fuse_en_sw_app_read_test | 101105409414743702945218926667474068819694390313711856436634600369636543081533 | None | ||
| chip_sw_entropy_src_csrng | 74694946833651558370529971460019597407771194636481623434601076048517910151098 | None | ||
| chip_sw_entropy_src_kat_test | 47150633915028502376647669674458707693257894171145387755244506596458650792969 | None | ||
| chip_sw_entropy_src_ast_rng_req | 97742989022460142485896441480216865906689228958671713169272605509059266713193 | None | ||
| chip_sw_hmac_enc | 107893437137768951789512791453634580696967604696382811039709865680154051660804 | None | ||
| chip_sw_hmac_enc_jitter_en | 104513075817632373849809569626647870395665156823874558524889998456702161448206 | None | ||
| chip_sw_hmac_enc_idle | 1402121033114974134900976502322959800256442098020088267348380274640852840473 | None | ||
| chip_sw_keymgr_dpe_key_derivation | 29415153037847028551527682737854901899779808797229524905081928727956000568474 | None | ||
| chip_sw_keymgr_dpe_key_derivation_prod | 85467914258314476209070326196463789334445179093368856769857001896425393797619 | None | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 32996520930389208287982616472674207762757040834422349670475528006853556938406 | None | ||
| chip_sw_kmac_mode_cshake | 84933897517779044051718768767557159318096020920728481562116102773763789847077 | None | ||
| chip_sw_kmac_mode_kmac | 61073292767019116077181484390091654181324712768813242051088900404174757460939 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en | 57888048681865072044784268276527159103924351350894411046986092143512278862512 | None | ||
| chip_sw_kmac_app_rom | 9440261367197109863690870875599028136768083268863511079304680783337201976642 | None | ||
| chip_sw_kmac_idle | 66110400150779888332051000949232558764184675712883240220474342868996346562128 | None | ||
| chip_sw_rom_ctrl_integrity_check | 55349550103420324683658293840936356500531566530343989399134039700042408038094 | None | ||
| chip_sw_sram_ctrl_scrambled_access | 48871508709322736184470116672751874573775211119750332057683248108241001607007 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 5000346087600041157105310704914553275282980243455354841261606188452620270396 | None | ||
| chip_sw_sram_ctrl_execution_main | 3958520811145617109631128140939505829066254486029128432094605706455182877974 | None | ||
| chip_sw_coremark | 109081418461532479529693784206455248646642408811442806624534175737742594931250 | None | ||
| chip_plic_all_irqs_0 | 71702708325799054663486804465318951782366932271918066356355866655525863188711 | None | ||
| chip_plic_all_irqs_10 | 75753458652387265053782428911895969983854420569600124457782823532386962981086 | None | ||
| chip_sw_plic_sw_irq | 24020140098834976928495085303796407456095411955855592745440152422954567121718 | None | ||
| chip_sw_clkmgr_off_aes_trans | 98468927420015357015682219852838252071629867444654970046144845168260213543024 | None | ||
| chip_sw_clkmgr_off_hmac_trans | 43781046110398998592499636013501931422367096167787305685656415420034761587363 | None | ||
| chip_sw_clkmgr_off_kmac_trans | 50439010698479281376342603149647370423858982844808158655154147521766528457516 | None | ||
| chip_sw_clkmgr_off_otbn_trans | 27617608639856866424239031546164650450018882736529689088390359576164276902538 | None | ||
| chip_sw_clkmgr_reset_frequency | 30724402205971950888220707801015796759021186195743402926113345734380055644515 | None | ||
| chip_sw_clkmgr_jitter | 66030817781457877974250788457201503496690973265292506951107148704548271418084 | None | ||
| chip_sw_clkmgr_sleep_frequency | 59285574152699430116220602288022922695885219394261522363369117142955205939314 | None | ||
| chip_jtag_csr_rw | 11799222546218234567010834164281961255494598476228526007077575759634291569746 | None | ||
| chip_jtag_mem_access | 26006167537108810789527813335839696021371480849794132694494578111860156408562 | None | ||
| chip_sw_ast_clk_outputs | 8489175017066716072142075996083938922529624610549575266341070732889973069660 | None | ||
| chip_sw_lc_ctrl_program_error | 1275814839254388353911793282853235629399418219179974329298701875965206343888 | None | ||
| chip_rv_dm_ndm_reset_req | 59940985878751314058006598619249891486833561885909208628522466522711641571409 | None | ||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 66116967324325912401635620181517232277208198077123926389496903900146545613328 | None | ||
| chip_sw_rv_dm_access_after_wakeup | 90949136052472937640164355470457678564141161556982198395881288816158442152626 | None | ||
| chip_sw_rv_dm_access_after_escalation_reset | 85344493458677201012897558540420586611784749417741112632663673121873083619723 | None | ||
| chip_sw_rv_core_ibex_address_translation | 100198943532310304335377153309223381252850615386184780943124145218289801501091 | None | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 99148024288527540724060538273494124753083189013779690270110706096710627653373 | None | ||
| chip_sw_rv_core_ibex_icache_invalidate | 81811693192770854763611859872136232150002806842225095758907319262736178028932 | None | ||
| chip_sw_clkmgr_jitter_reduced_freq | 97565406438521797831704667070353981311985185759040948704768620106372574841022 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 96980661806235529410533133031388044557859310203013324888676206405308086806612 | None | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 27808930432945505561169334582756693679499592031674405970292405150162629194538 | None | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 44588277502163171146580844249567658199919587519039635439985607633115992194614 | None | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 29360513878394674666726011716378714058478486051261081002731335385765626156062 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 17406760029653795111676817886843299589546436389503416860424085570785290326019 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 3873108974153004871184014644294891624857605213128756805208722731597638202230 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 35682962874968258328224982873027182256456937093459500106227735209825375230684 | None | ||
| chip_sw_power_virus | 50270683523924447556171048146642546873890330090335187937589361333785214682466 | None | ||
| chip_sw_dma_inline_hashing | 44685490929217949707784098773171111803057942212627994720711656643959097897472 | None | ||
| chip_sw_dma_abort | 79941474312979465472324837748626458246961656131756210818836759622419787724920 | None | ||
| base_rom_e2e_smoke | 54272522346842225109712844638182774687910291825193082287244820056444555288911 | None | ||
| rom_e2e_smoke | 7379729775091039046781550313388194634926776233546632765162760086978872830167 | None | ||
| rom_e2e_shutdown_exception_c | 84485821151624640108507747504481566964442133810476406936916073610362034213440 | None | ||
| rom_e2e_shutdown_output | 106957110947108851793282326782111791708929808690199019695298600131243571105832 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 50522801578812547152238151887988583248449041072019716423793874541080861857850 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 61504449796541865953607478797480117227441691534072059505192115818051598678695 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 18400826244835114798904924997656616030145469652138583998539129900406693101267 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 106904600983271680685835390738545680122483340393551409357150025224903558463095 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 82932081657204219024517672694972982669634854952965461740698686635164042250740 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 30922596586062958441897397019661625647273971058766639897005113433124372791648 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 37980203045796000561407771412981099029497173127202432056377370598655954821966 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 113594932248815922102471875867038534373435874988665148662222615502746967286253 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 363632011155017187711066473460272802675187635374474982027521008878383944868 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 95998076146843583028357819678256205655073909434891007966239405380242998697019 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 54362404977740256398548307083839197043865844119698474750736979995003690261623 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 36797658179367082170518264079404734949421260901071695526739104463418056487924 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 88955231893631848151643205793446473064681120985072769417481100613679358447037 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 14963134440584938687453467595230206388770298698734804545027106438291600393759 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 43501163253433587439582509087939909381274412441683915282436582078345219403019 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 86051794032460645259813504319077689390884647517746449647370657919772328666541 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 61471753743269641588143179959904996491498948642542683370347187197385285110963 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 53032693708185421175187304499165111700893464762675903249961175333199055452174 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 70106713582864005854332186715242177414231809094902126187043825246023973089060 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 10642544922799965061148289718251387883689657375248822596466578636598876432487 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 19088570650207566202034168667577645591627124127748599169625399120849200361497 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 89745584344628568111879563953041009945081774985262159168126248541387564959860 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 54188798176520787613154240162311250818050945414102757631321647853260302035546 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 2347005660491849296915986448601899840449159293482529743880796155488240872234 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 53344848837418180690212376404440083321664315017165825269149431217091973072625 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 96747373270134055834175086125668747247315034029121503015066030377445831695512 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 34257539323899011108626997241581091827864674965197024802941984017308663289372 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 457625896153092668942741225990593247715256643956204213065199500028018003702 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 15112791827472984315373158065229249369865066992102491870278116669491035923310 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 39116616860351318556141150155083444813632409432099940702012649217672391499822 | None | ||
| rom_e2e_asm_init_test_unlocked0 | 32143812460872168852392326491608564664752644300117398330618565618076718174333 | None | ||
| rom_e2e_asm_init_dev | 66342971592881140419094257610780226188628552660787562838627171422906417851677 | None | ||
| rom_e2e_asm_init_prod | 81625512318805143462425693755448286009370933457813254297051246468748293083575 | None | ||
| rom_e2e_asm_init_prod_end | 18634169085774095136270645456021936721824522151245453158784082740606804236846 | None | ||
| rom_e2e_asm_init_rma | 42772930796411180672821319625958737125302134302204476640676319165135813927473 | None | ||
| rom_e2e_jtag_debug_test_unlocked0 | 25655786310695586320538550074333684588875729884090966637913923520665385467009 | None | ||
| rom_e2e_jtag_debug_dev | 32801394469654465160949862625356884892089807169589211118653126318936723835101 | None | ||
| rom_e2e_jtag_debug_rma | 83099545411390897388946755566523609822849083329050095873093978615844663044095 | None | ||
| rom_e2e_jtag_inject_test_unlocked0 | 107993343642646168416094303551105999019359748667923322373865679220725400316835 | None | ||
| rom_e2e_jtag_inject_dev | 71056521669905756088005240460705358025618821787878738758024796369321661410920 | None | ||
| rom_e2e_jtag_inject_rma | 33128873046366135269384594279389192630076623272502339746986615799941648408224 | None | ||
| rom_e2e_static_critical | 54758014825893902559918710399416847180196381355738511334394788719081899737541 | None | ||
| rom_e2e_keymgr_init_rom_ext_meas | 69638535312445331018614874642825722704797072393443059022466029340452463640653 | None | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 86507978737514794646084095726956762327536922184368454140410352700662757846236 | None | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 43176430528702821058830760888497657288287002225652847912571313079499400566705 | None | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 18634310300525361241547070883581954626461358521239758391199087733236801558700 | None | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 79340449893098754436054856597415119176558182162563872413397383951660259298087 | None | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 40990260008745226830360166772687775782917476882305957250364761237482964276329 | None | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 76153803993730697423935062256839691531730980815194322783147889299516876361548 | None | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 75107562683533985226822739493532805394173455827266416193570351147598140314710 | None | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 16931657484455226155380570851754196805010932071035631189090365967105344912647 | None | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 64600279997232090277331199465718537526461989750732437779239335509492865268860 | None | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 110608636087627596544886158781178797192517407069575205738930733207783554214382 | None | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 62335971396123349872392091401106001458655206606622687122492564585147373766773 | None | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 61517794109087633159910424431111716615042701774901396328780862690566490687891 | None | ||
| rom_volatile_raw_unlock | 68746018025434817601505802962529306166434797584773413452355615699898439776144 | None | ||
| rom_raw_unlock | 11241255703756679380093671373817682330991509435439737875931515737102527961160 | None | ||
| rom_e2e_self_hash | 1746495467725069147930675873184323966834242913193318814783426110271522451848 | None | ||
| chip_sw_uart_smoketest_signed | 84842905841850337208068472368025532564783617712519293004059664774564206160390 | None | ||
| rom_keymgr_functest | 41402774242240575468173134829132332672033434811091506126764515740772785119390 | None | ||
| chip_sw_aes_smoketest | 76071701137136721335446927671268342644127837552232819390141278972877888918854 | None | ||
| chip_sw_aon_timer_smoketest | 60059503898922941981721604206594078293180756569660474598026915960340730588771 | None | ||
| chip_sw_clkmgr_smoketest | 11048092843499822185909041671579233522966477166956645684438965640392351359025 | None | ||
| chip_sw_csrng_smoketest | 37980628165879648358423590688732245839478631649906447634945041946834928629113 | None | ||
| chip_sw_entropy_src_smoketest | 19153255952736657804090364263362333746621291682588573413711088268708758420799 | None | ||
| chip_sw_gpio_smoketest | 71341766867107777667911690917865681027876584666131397280670109114228160088205 | None | ||
| chip_sw_hmac_smoketest | 92363037000216876799263803579330501948007573470111525970976751576840239924878 | None | ||
| chip_sw_kmac_smoketest | 91525878661712911966221147403916708175299332624439725388933270440553223767851 | None | ||
| chip_sw_mbx_smoketest | 115472355722174454787514534850507407798294614050273060775936308653722510492255 | None | ||
| chip_sw_otbn_smoketest | 175527044994619706017729691900460318812191439308728045057400691615054169359 | None | ||
| chip_sw_otp_ctrl_smoketest | 9048398308284415147596935257098011034272344087139251087634278101998660544897 | None | ||
| chip_sw_rv_plic_smoketest | 26362890958797632297382147349261729138479025199477194031330503569891348895440 | None | ||
| chip_sw_rv_timer_smoketest | 81154071044589453174098375181060470016022062796444611754069931494665373756603 | None | ||
| chip_sw_rstmgr_smoketest | 41003907342772623324498569698638158161544047427590457228681698076386889657150 | None | ||
| chip_sw_sram_ctrl_smoketest | 23619545622912361024470319575448118857569988656491639800083521871385003429078 | None | ||
| chip_sw_uart_smoketest | 21250653806649540990510363571774398648988201671793417977218574457612337747640 | None | ||
| xbar_smoke | 104151291830990874228781467289028987631836487000767787289954458679602931641024 | None | ||
| xbar_smoke_zero_delays | 23707456083564309185025899740428779612257329152589053588780997844231263880349 | None | ||
| xbar_smoke_large_delays | 19451312974320984092246643057323258778685262112891139937558566882806918171423 | None | ||
| xbar_smoke_slow_rsp | 102354912401913720931776790992463536841101469805308386297536647761927047611745 | None | ||
| xbar_random | 61968567682871168760439331019068660947057611141965965738619097182164893003288 | None | ||
| xbar_random_zero_delays | 30949587693819868220939430734202575052409346782259298217834292982664970747995 | None | ||
| xbar_random_large_delays | 47170252357127123461529931766763184751183922990142987304446053496754319302011 | None | ||
| xbar_random_slow_rsp | 33740807685049342863719291501149863598005120795028888667030576656242341139029 | None | ||
| xbar_access_same_device | 31016806265052748073901525624891615973211261812642715157463902274715237456121 | None | ||
| xbar_access_same_device_slow_rsp | 26313858644271016065011724318780138934923307686122305427765377049981377905834 | None | ||
| xbar_same_source | 105480269352979688263756981360798728973160972797919467362562579481507374818056 | None | ||
| xbar_error_random | 27710755951367156180975415174617044681708781118043103175687510791558292996010 | None | ||
| xbar_unmapped_addr | 96519735658521388821600169548638695033100597253722324520857837197397416793449 | None | ||
| xbar_error_and_unmapped_addr | 108108926494361139300323832539018338197881458723574147110758895761410488179514 | None | ||
| xbar_stress_all | 92706627204527326358169338624403566813562359243753142343142254207351904648291 | None | ||
| xbar_stress_all_with_rand_reset | 78255435045395183661712014485722652956143207958318683965835954843459409244677 | None | ||
| xbar_stress_all_with_error | 92500614834356086745552179010332210333382873764171958598016829737875858022294 | None | ||
| xbar_stress_all_with_reset_error | 62454353456649385648884682048073142372697990980187219469068173992824636148279 | None | ||
| chip | None | None | ||
| chip | None | None | ||