Simulation Results: edn/edn0

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.750s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 0.000us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.410s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.940s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 0.000us 1 1 100.00
edn_csr_aliasing 0.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.050s 0.000us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.050s 0.000us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.050s 0.000us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 0.000us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.880s 0.000us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 0.000us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 0.000us 1 1 100.00
edn_disable_auto_req_mode 0.960s 0.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.140s 0.000us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 0.000us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.720s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.970s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.970s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 0.000us 1 1 100.00
edn_csr_rw 0.750s 0.000us 1 1 100.00
edn_csr_aliasing 0.940s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.880s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 0.000us 1 1 100.00
edn_csr_rw 0.750s 0.000us 1 1 100.00
edn_csr_aliasing 0.940s 0.000us 1 1 100.00
edn_same_csr_outstanding 0.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.290s 0.000us 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 0.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.880s 0.000us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.880s 0.000us 1 1 100.00
edn_sec_cm 6.270s 0.000us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.880s 0.000us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.290s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
edn_stress_all_with_rand_reset 97441100476013106752287249024216395347448770608053227743799417842918580978806 None
Job timed out after 180 minutes
Job returned non-zero exit code
edn None None
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:110: cov_merge] Error 1
Job killed most likely because its dependent job failed.
edn None None