Simulation Results: gpio

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.18 %
  • code
  • 68.06 %
  • assert
  • 93.99 %
  • func
  • 99.50 %
  • line
  • 86.59 %
  • branch
  • 77.48 %
  • cond
  • 73.31 %
  • toggle
  • 93.52 %
  • FSM
  • 9.38 %
Validation stages
V1
36.36%
V2
50.00%
V2S
33.33%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 4 4 100.00
gpio_smoke 1.070s 0.000us 1 1 100.00
gpio_smoke_no_pullup_pulldown 1.020s 0.000us 1 1 100.00
gpio_smoke_en_cdc_prim 0.830s 0.000us 1 1 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.020s 0.000us 1 1 100.00
csr_hw_reset 0 1 0.00
gpio_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
gpio_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
gpio_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
gpio_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
gpio_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
gpio_csr_rw 0.000s 0.000us 0 1 0.00
gpio_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 2 2 100.00
gpio_random_dout_din 1.000s 0.000us 1 1 100.00
gpio_random_dout_din_no_pullup_pulldown 0.730s 0.000us 1 1 100.00
out_in_regs_read_write 1 1 100.00
gpio_dout_din_regs_random_rw 0.710s 0.000us 1 1 100.00
gpio_interrupt_programming 1 1 100.00
gpio_intr_rand_pgm 1.020s 0.000us 1 1 100.00
random_interrupt_trigger 1 1 100.00
gpio_rand_intr_trigger 2.340s 0.000us 1 1 100.00
interrupt_and_noise_filter 1 1 100.00
gpio_intr_with_filter_rand_intr_event 1.820s 0.000us 1 1 100.00
noise_filter_stress 1 1 100.00
gpio_filter_stress 16.130s 0.000us 1 1 100.00
regs_long_reads_and_writes 1 1 100.00
gpio_random_long_reg_writes_reg_reads 3.070s 0.000us 1 1 100.00
full_random 1 1 100.00
gpio_full_random 0.850s 0.000us 1 1 100.00
stress_all 1 1 100.00
gpio_stress_all 75.380s 0.000us 1 1 100.00
alert_test 1 1 100.00
gpio_alert_test 0.570s 0.000us 1 1 100.00
intr_test 0 1 0.00
gpio_intr_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
gpio_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
gpio_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
gpio_csr_rw 0.000s 0.000us 0 1 0.00
gpio_same_csr_outstanding 0.000s 0.000us 0 1 0.00
gpio_csr_aliasing 0.000s 0.000us 0 1 0.00
gpio_csr_hw_reset 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
gpio_csr_rw 0.000s 0.000us 0 1 0.00
gpio_same_csr_outstanding 0.000s 0.000us 0 1 0.00
gpio_csr_aliasing 0.000s 0.000us 0 1 0.00
gpio_csr_hw_reset 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
gpio_tl_intg_err 0.000s 0.000us 0 1 0.00
gpio_sec_cm 0.820s 0.000us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
gpio_tl_intg_err 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 0 1 0.00
gpio_rand_straps 62.292s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
gpio_stress_all_with_rand_reset 0.560s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
gpio_inp_prd_cnt 0.530s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
cover_reg_top None None
recompiling module tb
All of 69 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 15.162 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
gpio_rand_straps 69504928067330434540376630119740746071545485577595570196372945946072740023814 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:34 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
Job killed most likely because its dependent job failed.
gpio_csr_rw 62578710172674613273144455579162083032118810454817343561814395366329600472228 None
gpio_same_csr_outstanding 6107457824589682828515460674834237730486533318236048515078088365034140062818 None
gpio_csr_aliasing 37551274252313149653062448203125930559807523185465621519246073544915447903742 None
gpio_csr_mem_rw_with_rand_reset 104455062217045476953131025424103515319657397400723256616138066550457047119873 None
gpio_tl_intg_err 10901683938308379444261592010383482300575366919965596077630160946014317574082 None
gpio_tl_errors 38138858843874072077437301384410831646433759685586096235938743045137774511226 None
gpio_intr_test 14788207703670776280224158690787028039372001929879591676444784837552375309166 None
gpio_csr_hw_reset 103328666331676999535738625231765658659012987464394745449714934412853905233617 None
gpio_csr_bit_bash 41224273920888534474609893662426298807994113598155564475222743913319259194897 None
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -*
gpio_stress_all_with_rand_reset 21246423501887133065485593106838835182399551923496598483396642061145434145699 78
UVM_FATAL @ 9660307 ps: uvm_test_top.env.m_tl_agent_gpio_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 9660307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---