| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| hmac_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| hmac_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg | 0 | 1 | 0.00 | |||
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| back_pressure | 0 | 1 | 0.00 | |||
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_vectors | 0 | 6 | 0.00 | |||
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| burst_wr | 0 | 1 | 0.00 | |||
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| datapath_stress | 0 | 1 | 0.00 | |||
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wipe_secret | 0 | 1 | 0.00 | |||
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| save_and_restore | 0 | 6 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| fifo_empty_status_interrupt | 0 | 11 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wide_digest_configurable_key_length | 0 | 14 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| hmac_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| hmac_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| hmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| hmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| write_config_and_secret_key_during_msg_wr | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_reset | 0 | 1 | 0.00 | |||
| hmac_stress_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| hmac_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| hmac_directed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
recompiling module tb
All of 81 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 14.817 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| cover_reg_top | None | None |
recompiling module tb
All of 80 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 14.348 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| hmac_smoke | 31264586110309481611039104436927532552260889640164693103358834858728958755462 | None | ||
| hmac_long_msg | 17390700850515713253352659763055433094773960608265878924203012274107297693348 | None | ||
| hmac_stress_reset | 91136202543046404709228876147168928297342087979365862842001811157772956530666 | None | ||
| hmac_back_pressure | 41013965606631998207473699882378164940006041215352705092678243506264514581143 | None | ||
| hmac_datapath_stress | 86304619007891965200035207337796292662586404373984782441208355239236763723830 | None | ||
| hmac_burst_wr | 99065645210474083832737781235116883303779880905478274247796222249929853456084 | None | ||
| hmac_error | 102065505342222439693702045563052784915936555376720308811765958009006558151871 | None | ||
| hmac_wipe_secret | 80832557703439711745187767604102248550332803609703423693226771728706898427056 | None | ||
| hmac_test_sha256_vectors | 8964748684986586162495268361226364684686907885352200745740134553933027019743 | None | ||
| hmac_test_sha384_vectors | 4091788023343669397091315413851286090066178358294101196373147540087396181646 | None | ||
| hmac_test_sha512_vectors | 46679646414216731971607789789112058928052844855228588511667345277199698537456 | None | ||
| hmac_test_hmac256_vectors | 86478232441064286334406242951998167110781037381719848756279573841278324797538 | None | ||
| hmac_test_hmac384_vectors | 109193252683544640203705740013482725657328162903345192078976765997743746917249 | None | ||
| hmac_test_hmac512_vectors | 114272578628304226042299923996695233541326480346149663101187691562440197511782 | None | ||
| hmac_stress_all | 89800241591911385769685868926942402655694370848202279250638347023613161315236 | None | ||
| hmac_stress_all_with_rand_reset | 5435447473668415676251353177043115247020213227357607518930157982151667082783 | None | ||
| hmac_directed | 55921825461534128736501116259334545055515299456509891927301596576160112064176 | None | ||
| hmac_sec_cm | 58288076353778939394452799072110886014452007646774591284384347932113146531967 | None | ||
| hmac_alert_test | 33658313707493620912314923627425078544640936798532316627831745747360221809804 | None | ||
| hmac_tl_errors | 90888570472420963902609662389463713421465143851213332627520341576703609204444 | None | ||
| hmac_tl_intg_err | 115500883728461580674898604041388457254073568813979765263759133926807936236572 | None | ||
| hmac_intr_test | 99293460506700684271667562992772581701994216363298854783475468493783157681434 | None | ||
| hmac_csr_hw_reset | 33660380442145956891373445704159035350434742384049210726114331421816426595898 | None | ||
| hmac_csr_rw | 15546535365975873371391279521299329595472221956793561178564446205953153630109 | None | ||
| hmac_csr_bit_bash | 76003060316870597282662251067157599339647695397943163421237119705487001582872 | None | ||
| hmac_csr_aliasing | 12243453936727974686085760442605758487166985408985050254603723563547380466862 | None | ||
| hmac_same_csr_outstanding | 15022667195179153712817275912448054977708929879744087972405071562056524160272 | None | ||
| hmac_csr_mem_rw_with_rand_reset | 23724433487997482887830393093216528205387122186538729166189894259065914977903 | None | ||
| hmac | None | None | ||
| hmac | None | None | ||