Simulation Results: keymgr

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Validation stages
V1
100.00%
V2
87.50%
V2S
94.74%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.300s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 4.290s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.950s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.060s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 2.790s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.110s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
keymgr_csr_aliasing 2.790s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 24.160s 0.000us 1 1 100.00
sideload 3 4 75.00
keymgr_sideload 3.510s 0.000us 1 1 100.00
keymgr_sideload_kmac 3.100s 0.000us 1 1 100.00
keymgr_sideload_aes 1.920s 0.000us 1 1 100.00
keymgr_sideload_otbn 11.911s 0.000us 0 1 0.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.950s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.150s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.520s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 38.540s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.410s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.950s 0.000us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 7.320s 0.000us 1 1 100.00
intr_test 0 1 0.00
keymgr_intr_test 11.903s 0.000us 0 1 0.00
alert_test 0 1 0.00
keymgr_alert_test 35.877s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.490s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.490s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.950s 0.000us 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
keymgr_csr_aliasing 2.790s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.700s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.950s 0.000us 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
keymgr_csr_aliasing 2.790s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 2.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
tl_intg_err 1 2 50.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
keymgr_tl_intg_err 36.763s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.350s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.350s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.350s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.350s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.800s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
keymgr_tl_intg_err 36.763s 0.000us 0 1 0.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.350s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 24.160s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.290s 0.000us 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.290s 0.000us 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.290s 0.000us 1 1 100.00
keymgr_csr_rw 0.840s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.150s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.410s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.410s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.290s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.370s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.150s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.150s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.150s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.150s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.150s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 12.070s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.150s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.350s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
keymgr_sideload_otbn 17583711790936185775493639720632872563609795067183123616400578650592530299349 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:46 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
keymgr_alert_test 79785587874292133541482542358369010566797119486572762793692589033685623021297 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:46 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
keymgr_tl_intg_err 3325832328150979220217737250492604359253259127193244301847885649602412983868 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:47 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
keymgr_intr_test 10335223223686985195098948842926498823258710209842071734204180302859601749840 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:47 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
keymgr None None
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-elfile needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:115: cov_report] Error 1
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 78623122652114420020274299589967498241589183093670627644388432049342575377090 162
UVM_ERROR @ 129920655 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 129920655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---