Simulation Results: keymgr_dpe

 
18/03/2026 16:32:16 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 50.27 %
  • code
  • 44.65 %
  • assert
  • 96.68 %
  • func
  • 9.48 %
  • line
  • 54.66 %
  • branch
  • 63.23 %
  • cond
  • 61.76 %
  • toggle
  • 43.58 %
  • FSM
  • 0.00 %
Validation stages
V1
62.50%
V2
75.00%
V2S
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
keymgr_dpe_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.840s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.670s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.370s 0.000us 1 1 100.00
csr_aliasing 0 1 0.00
keymgr_dpe_csr_aliasing 34.160s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.080s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
keymgr_dpe_csr_rw 0.670s 0.000us 1 1 100.00
keymgr_dpe_csr_aliasing 34.160s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.690s 0.000us 1 1 100.00
alert_test 0 1 0.00
keymgr_dpe_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.480s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.480s 0.000us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
keymgr_dpe_csr_hw_reset 0.840s 0.000us 1 1 100.00
keymgr_dpe_csr_rw 0.670s 0.000us 1 1 100.00
keymgr_dpe_csr_aliasing 34.160s 0.000us 0 1 0.00
keymgr_dpe_same_csr_outstanding 1.930s 0.000us 1 1 100.00
tl_d_partial_access 3 4 75.00
keymgr_dpe_csr_hw_reset 0.840s 0.000us 1 1 100.00
keymgr_dpe_csr_rw 0.670s 0.000us 1 1 100.00
keymgr_dpe_csr_aliasing 34.160s 0.000us 0 1 0.00
keymgr_dpe_same_csr_outstanding 1.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
keymgr_dpe_tl_intg_err 4.660s 0.000us 1 1 100.00
keymgr_dpe_sec_cm 0.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 1.170s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_dpe_shadow_reg_errors 1.170s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 1.170s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_dpe_shadow_reg_errors 1.170s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 3.590s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
keymgr_dpe_sec_cm 0.000s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
keymgr_dpe_sec_cm 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
default None None
recompiling module keymgr_dpe_cov_bind
All of 111 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 24.759 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
keymgr_dpe_csr_aliasing 52139840796427500422876813135345114879468821613780861471235941295052745213481 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Mar 18 16:38 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
Job killed most likely because its dependent job failed.
keymgr_dpe_smoke 75499534977943879458050969435967572533805799717792476042082205225431522329963 None
keymgr_dpe_sec_cm 31070503973204559255288380665280507534520778990058666588201055005417536124567 None
keymgr_dpe_alert_test 62714083361168914411756141913545587994208002126714614459992894740986864747820 None